PIXEL DRIVING CIRCUIT AND DISPLAY PANEL
    2.
    发明公开

    公开(公告)号:US20240144884A1

    公开(公告)日:2024-05-02

    申请号:US18274958

    申请日:2022-07-01

    Abstract: Provided are a pixel driving circuit and a display panel. The pixel driving circuit includes: a data writing sub-circuit, a threshold compensation sub-circuit, a driving sub-circuit, a storage sub-circuit, a first reset sub-circuit, a second reset sub-circuit. The driving sub-circuit and the storage sub-circuit are connected at a first node; the data writing sub-circuit and the storage sub-circuit are connected at a second node; the first reset sub-circuit includes a first transistor having a control electrode connected with a first reset signal line, a first electrode connected with a first initialization signal line, and a second electrode connected with the first node; the threshold compensation sub-circuit includes a second transistor having a first electrode connected with the first node, a second electrode connected with the second node, and a control electrode connected with a second scan line; the first transistor and/or the second transistor includes an oxide thin film transistor.

    DISPLAY SUBSTRATE AND DISPLAY DEVICE
    3.
    发明公开

    公开(公告)号:US20240290271A1

    公开(公告)日:2024-08-29

    申请号:US18044967

    申请日:2022-06-29

    CPC classification number: G09G3/3258 G09G2300/0426

    Abstract: A display substrate includes a driving module arranged on the base substrate, the driving module includes a plurality of driving units, and the driving unit includes a plurality of stages of driving circuits; the driving unit includes a first signal line, and the driving circuit includes an output sub-circuit; the display substrate includes at least two metal layers stacked along a direction away from the base substrate; in at least one driving unit, an orthographic projection of the first signal line on the base substrate at least partially overlaps an orthographic projection of a first electrode or a second electrode of at least one transistor included in the output sub-circuit on the base substrate, the first electrode and the second electrode are arranged on the same metal layer, and the first electrode and the first signal line are arranged on different metal layers.

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