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1.发明授权公开(公告)号：US12063808B2
公开(公告)日：2024-08-13
申请号：US17393661
申请日：2021-08-04
Inventor： Jun Liu , Jingang Fang , Yang Zhang , Tongshang Su , Wei He , Bin Zhou , Ning Liu
IPC: H10K50/844 , H10K59/124 , H10K59/131 , H10K59/17 , H10K71/00 , H10K59/12
CPC classification number: H10K50/844 , H10K59/124 , H10K59/131 , H10K59/17 , H10K71/00 , H10K59/1201
Abstract: A light-emitting substrate includes; a base, an isolation portion disposed on the base and located in an isolation region located outside a light-emitting region, and a second insulating pattern located in the light-emitting region. The isolation portion includes a first conductive pattern, a second conductive pattern and a first insulating pattern that are sequentially stacked on the base; an orthogonal projection of the first conductive pattern on the base is located within an orthogonal projection of the second conductive pattern on the base; and a side face of the first conductive pattern proximate to the light-emitting region and a corresponding side face of the second conductive pattern proximate to the light-emitting region have a first gap therebetween. A side face of the second insulating pattern proximate to the first insulating pattern and a side face of the first insulating pattern proximate to the second insulating pattern have a second gap therebetween.
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公开(公告)号：US11930677B2
公开(公告)日：2024-03-12
申请号：US17329349
申请日：2021-05-25
Inventor： Yongchao Huang , Can Yuan , Liusong Ni , Chao Wang , Jiawen Song , Zhiwen Luo , Jun Liu , Leilei Cheng , Qinghe Wang , Tao Sun
IPC: H10K59/131 , H10K59/12 , H10K59/126 , H10K59/38 , H10K71/00
CPC classification number: H10K59/1315 , H10K59/126 , H10K59/38 , H10K71/00 , H10K59/1201
Abstract: A display panel and a fabricating method thereof, and a displaying device. The display panel includes a substrate, a resistance reducing trace, an inter-layer-medium layer and a signal line. The substrate is divided into a plurality of sub-pixel regions and a pixel separating region. The resistance reducing trace is provided on the pixel separating region of the substrate. The inter-layer-medium layer is provided on the substrate, and the inter-layer-medium layer has an opening exposing the resistance reducing trace. The signal line is provided within the opening, the signal line is connected to the resistance reducing trace, the signal line is distributed in a column direction along the display panel, and in a row direction along the display panel, a width of the opening is greater than or equal to a width of the signal line.
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公开(公告)号：US11672147B2
公开(公告)日：2023-06-06
申请号：US16652487
申请日：2019-05-16
Inventor： Wei Li , Bin Zhou , Jun Liu , Ning Liu , Wei Song , Xuehai Gui , Xiaodong Zhang , Rong Liu
CPC classification number: H01L27/3246 , H01L27/3283 , H01L51/56
Abstract: The present application discloses a display substrate. The display substrate may include a base substrate; a plurality of first electrodes arranged in an array on the base substrate; and a pixel defining layer defining a plurality of openings on the base substrate. The plurality of openings may overlap the plurality of first electrodes respectively. The pixel defining layer may include a plurality of first pixel defining units and a plurality of second pixel defining units; and the plurality of first pixel defining units may be separated from one another.
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公开(公告)号：US11569307B2
公开(公告)日：2023-01-31
申请号：US17043962
申请日：2020-04-22
Inventor： Jun Liu , Liangchen Yan , Bin Zhou , Wei Li , Tongshang Su , Yongchao Huang , Biao Luo , Xuehai Gui
Abstract: An array substrate is provided, including a base substrate, a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode that are sequentially provided, and further including a first insulating layer, a second insulating layer, a third insulating layer, at least one first via, and at least one second via. Each first via penetrates through the third insulating layer, and in each pixel unit with plural chromatic color resists, each first via is between adjacent two chromatic color resists and filled by one of the adjacent two chromatic color resists. Each second via penetrates through the second insulating layer, the at least one second via is in one-to-one correspondence with the at least one first via, each second via is filled by a chromatic color resist having a same color as that of the chromatic color resist in the corresponding first via.
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公开(公告)号：US11537016B2
公开(公告)日：2022-12-27
申请号：US16964278
申请日：2019-12-13
Inventor： Leilei Cheng , Jingang Fang , Luke Ding , Jun Liu , Wei Li , Bin Zhou
IPC: G02F1/1333 , G02F1/1362 , H01L21/768 , H01L23/532 , H01L27/12
Abstract: A method of manufacturing an array substrate is provided, which comprises: forming a first metal layer and an insulating layer in sequence on a base substrate, the insulating layer covering the first metal layer; forming an etch barrier layer on the insulating layer; etching the etching barrier layer and the insulating layer multiple times, wherein an effective blocking area of the etching barrier layer decreases successively in each etching to form a connection hole penetrating the insulating layer, the connection hole includes a plurality of via holes connected in sequence, and a slope angle of a hole wall of each via hole is smaller than a preset slope angle; and forming a second metal layer, the second metal layer being connected to the first metal layer through the connection hole.
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Patent Agency Ranking
公开(公告)号：US11462602B2
公开(公告)日：2022-10-04
申请号：US16905899
申请日：2020-06-18
Inventor： Yongchao Huang , Jun Cheng , Dongfang Wang , Jun Liu , Leilei Cheng , Liangchen Yan
Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a first signal line on the base substrate; a first buffer layer provided on the base substrate and covering the first signal line; a second signal line on a side of the first buffer layer facing away from the base substrate; a first insulating layer provided on the base substrate and covering the second signal line; and a thin film transistor on a side of the first insulating layer facing away from the base substrate, the thin film transistor including a gate electrode, a source electrode and a drain electrode. A thickness of the first signal line is greater than that of the gate electrode, and a thickness of the second signal line is greater than that of the source electrode or the drain electrode.
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7.发明授权公开(公告)号：US11380796B2
公开(公告)日：2022-07-05
申请号：US16638283
申请日：2019-08-07
Inventor： Tongshang Su , Dongfang Wang , Jun Liu , Guangyao Li , Wei Li , Qinghe Wang , Chao Wang , Tao Sun
IPC: H01L29/786 , H01L27/12 , H01L29/417 , H01L29/66 , H01L27/32
Abstract: The disclosure relates to a thin film transistor. The thin film transistor may include a substrate, an active layer on the substrate, a gate on the active layer, and a source and a drain. The active layer may include a first conducting region, a second conducting region, and a channel region between the first conducting region and the second conducting region. An orthographic projection of the source and an orthographic projection of the drain on the substrate may cover at least an orthographic projection of a first conducting region and an orthographic projection of a second conducting region on the substrate.
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公开(公告)号：US11355647B2
公开(公告)日：2022-06-07
申请号：US16331008
申请日：2018-08-17
Inventor： Yingbin Hu , Ce Zhao , Dongfang Wang , Bin Zhou , Jun Liu , Yuankui Ding , Wei Li
IPC: H01L27/00 , H01L29/00 , H01L29/786 , H01L27/12 , H01L29/66 , G02F1/1368 , H01L27/32
Abstract: A thin film transistor includes an active layer, a source electrode and a drain electrode. The active layer includes a conductive region and the conductive region is between the source electrode and the drain electrode and is spaced apart from at least one of the source electrode and the drain electrode.
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公开(公告)号：US20220093893A1
公开(公告)日：2022-03-24
申请号：US17336523
申请日：2021-06-02
Inventor： Yang Zhang , Ning Liu , Bin Zhou , Leilei Cheng , Liangchen Yan , Jun Liu , Qinghe Wang , Tao Sun , Zhiwen Luo
Abstract: A method for manufacturing a display panel includes: sequentially forming a conductive pattern, a light-emitting layer and a cathode layer on a substrate. The conductive pattern is formed by a one-time patterning process, and includes an auxiliary electrode layer. In a direction parallel to the substrate, both the first protective electrode and the second protective electrode in the auxiliary electrode layer extend over the metal electrode, a second orthographic projection of the second protective electrode on the substrate is within a first orthographic projection of the first protective electrode on the substrate, and an outer boundary of the second orthographic projection is staggered from an outer boundary of the first orthographic projection. The cathode layer is in contact with the first protective electrode and a sidewall of the metal electrode.
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公开(公告)号：US11264411B2
公开(公告)日：2022-03-01
申请号：US16928562
申请日：2020-07-14
Inventor： Tongshang Su , Dongfang Wang , Jun Liu , Qinghe Wang , Jun Wang , Ning Liu , Guangyao Li
IPC: H01L23/552 , H01L27/12
Abstract: An array substrate and a display device are provided in embodiments of the present disclosure. The array substrate includes a base substrate, a buffer layer, an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source-drain electrode electrically conductive layer, a passivation layer, and a first light shielding layer. The first light shielding layer is disposed on a side of the passivation layer facing away from the interlayer insulating layer. An orthographic projection of the first light shielding layer on the base substrate at least partially overlaps with an orthographic projection of the active layer on the base substrate, and the first light shielding layer is formed by a photoresist material.
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