公开(公告)号：US06176611B1

公开(公告)日：2001-01-23

申请号：US08906089

申请日：1997-08-05

申请人： Asaf Schushan ,  Yona Leshets

发明人： Asaf Schushan ,  Yona Leshets

IPC分类号： G04B1720

CPC分类号： G04G19/00 ,  G04F1/005

摘要： A timer for measuring a time period including a high frequency generating unit, a low frequency generating unit and a controller connected to the high and low frequency generating units, wherein the controller deactivates the high frequency generating unit during at least a portion of the time period, detects and counts predetermined portions of the signals provided by the high and low frequency generating units and counts a plurality of the portions of the currently active frequency generating unit.

摘要翻译： 一种用于测量包括高频产生单元，低频产生单元和连接到高频和低频发生单元的控制器的时间段的定时器，其中控制器在时间段的至少一部分期间停用高频产生单元 检测并计数由高低频发生单元提供的信号的预定部分，并对当前有效频率产生单元的多个部分进行计数。

公开(公告)号：US06411830B1

公开(公告)日：2002-06-25

申请号：US09161309

申请日：1998-09-28

申请人： Ram Alon ,  David Ben-Eli ,  Asaf Schushan ,  Yona Leshets

发明人： Ram Alon ,  David Ben-Eli ,  Asaf Schushan ,  Yona Leshets

IPC分类号： H04B7216

摘要： A timer for measuring a time period including a high frequency generating unit, a low frequency generating unit and a controller connected to the high and low frequency generating units, wherein the controller deactivates the high frequency generating unit during at least a portion of the time period, detects and counts predetermined portions of the signals provided by the high and low frequency generating units and counts a plurality of the portions of the currently active frequency generating unit.

公开(公告)号：US06946981B1

公开(公告)日：2005-09-20

申请号：US10745623

申请日：2003-12-29

申请人： Shiri Zilberman ,  Asaf Schushan ,  Yaron Aharoni ,  Doron Rainish

发明人： Shiri Zilberman ,  Asaf Schushan ,  Yaron Aharoni ,  Doron Rainish

IPC分类号： H03G3/30 ,  H04J13/04 ,  H03M7/00

CPC分类号： H04J13/00 ,  H03G3/3042

摘要： Briefly, an apparatus that may include scrambler to scramble data bits and control bit and filters to filter the scrambled data bits and control bits. The apparatus may also include a processor to adjust the gains of the filters.

摘要翻译： 简而言之，一种可以包括扰频器来扰乱数据比特并控制比特和滤波器以过滤加扰数据比特和控制比特的装置。 该装置还可以包括调节滤波器的增益的处理器。

公开(公告)号：US09336112B2

公开(公告)日：2016-05-10

申请号：US13592514

申请日：2012-08-23

申请人： Asaf Schushan ,  Barak Rotbard

发明人： Asaf Schushan ,  Barak Rotbard

IPC分类号： G06F3/00 ,  G06F11/30 ,  G06F13/16 ,  G06F3/06

CPC分类号： G06F11/3037 ,  G06F3/0613 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0683 ,  G06F11/3055 ,  G06F13/1678 ,  G06F13/1684

摘要： An apparatus includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a bus that includes a plurality of parallel data lines. The processor is configured to request the memory devices to provide respective status reports, and to receive the status reports from the memory devices such that, in a given clock cycle of the bus, the multiple status reports from the respective memory devices are received in parallel over respective different subsets of the data lines of the bus.

摘要翻译： 一种装置包括接口和处理器。 该接口被配置为通过包括多个并行数据线的总线与多个存储器设备进行通信。 处理器被配置为请求存储器设备提供相应的状态报告，并且从存储器设备接收状态报告，使得在总线的给定时钟周期中，并行地接收来自各个存储器设备的多个状态报告 在总线的数据线的不同子集上。

公开(公告)号：US20130339638A1

公开(公告)日：2013-12-19

申请号：US13589592

申请日：2012-08-20

申请人： Tal Lazmi ,  Asaf Schushan ,  Asaf Bart

发明人： Tal Lazmi ,  Asaf Schushan ,  Asaf Bart

IPC分类号： G06F12/00

CPC分类号： G06F13/1684

摘要： Apparatus includes multiple memory devices and a memory controller. The memory controller is configured to store and retrieve data by communicating with the memory devices over a first bus interface, and to query a status of the memory devices by communicating with the memory devices over a second bus interface that is separate from the first bus interface.

摘要翻译： 装置包括多个存储器装置和存储器控制器。 存储器控制器被配置为通过在第一总线接口上与存储器件进行通信来存储和检索数据，并且通过与第一总线接口分离的第二总线接口与存储器设备进行通信来查询存储器设备的状态 。

公开(公告)号：US20130339555A1

公开(公告)日：2013-12-19

申请号：US13592514

申请日：2012-08-23

申请人： Asaf Schushan ,  Barak Rotbard

发明人： Asaf Schushan ,  Barak Rotbard

IPC分类号： G06F3/00

CPC分类号： G06F11/3037 ,  G06F3/0613 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0683 ,  G06F11/3055 ,  G06F13/1678 ,  G06F13/1684

摘要： An apparatus includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a bus that includes a plurality of parallel data lines. The processor is configured to request the memory devices to provide respective status reports, and to receive the status reports from the memory devices such that, in a given clock cycle of the bus, the multiple status reports from the respective memory devices are received in parallel over respective different subsets of the data lines of the bus.

摘要翻译： 一种装置包括接口和处理器。 接口被配置为通过包括多个并行数据线的总线与多个存储器设备进行通信。 处理器被配置为请求存储器设备提供相应的状态报告，并且从存储器设备接收状态报告，使得在总线的给定时钟周期中，并行地接收来自各个存储器设备的多个状态报告 在总线的数据线的不同子集上。