公开(公告)号：US11494190B2

公开(公告)日：2022-11-08

申请号：US17218371

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Zachary Allen Kingsbury ,  Kurt Matthew Fellows ,  Thomas Gilles Tarridec

IPC: G06F9/38 ,  G06F9/30

Abstract: Instruction decoder circuitry decodes processing instructions each generating an output multi-bit data item in a destination architectural register by applying a processing operation to source data item(s) in respective source architectural register(s). The decoder circuitry detects whether an instruction defines a predicated merge operation that propagates a set of zero or more portions of the prevailing contents of the destination architectural register as respective portions of the output multi-bit data item. The portions are defined by predicate data. Register allocation circuitry associates physical registers with the destination architectural register and the source architectural register(s). When detector circuitry detects that an instruction defines a predicated merge operation, the register allocation circuitry associates a further physical register with that instruction to store a copy of the prevailing contents. In response to a state of generated predicate data, predicate detector circuitry controls association of the further physical register with the instruction.

公开(公告)号：US11327791B2

公开(公告)日：2022-05-10

申请号：US16546752

申请日：2019-08-21

Applicant: Arm Limited

Inventor： Michael David Achenbach ,  Robert Greg McDonald ,  Nicholas Andrew Pfister ,  Kelvin Domnic Goveas ,  Michael Filippo ,  . Abhishek Raja ,  Zachary Allen Kingsbury

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/52 ,  G06F9/50 ,  G06F9/30

Abstract: An apparatus provides an issue queue having a first section and a second section. Each entry in each section stores operation information identifying an operation to be performed. Allocation circuitry allocates each item of received operation information to an entry in the first section or the second section. Selection circuitry selects from the issue queue, during a given selection iteration, an operation from amongst the operations whose required source operands are available. Availability update circuitry updates source operand availability for each entry whose operation information identifies as a source operand a destination operand of the selected operation in the given selection iteration. A deferral mechanism inhibits from selection, during a next selection iteration, any operation associated with an entry in the second section whose source operands are now available due to that operation having as a source operand the destination operand of the selected operation in the given selection iteration.