公开(公告)号：US20220181201A1

公开(公告)日：2022-06-09

申请号：US17110826

申请日：2020-12-03

Applicant: Applied Materials, Inc.

Inventor： Yi XU ,  Yufei HU ,  He REN ,  Yu LEI ,  Shi YOU ,  Kazuya DAITO

IPC: H01L21/768

Abstract: Embodiments of the disclosure provide methods which reduce or eliminate lateral growth of a selective tungsten layer. Further embodiments provide an integrated clean and deposition method which improves the selectivity of selectively deposited tungsten on trench structures. Additional embodiments provide methods for forming a more uniform and selective bottom-up gap fill for trench structures with improved film properties.

公开(公告)号：US20210062330A1

公开(公告)日：2021-03-04

申请号：US17002296

申请日：2020-08-25

Applicant: APPLIED MATERIALS, INC.

Inventor： Wenjing XU ,  Yufei HU ,  Gang SHEN ,  Feng CHEN

IPC: C23C16/06 ,  C23C16/52 ,  C23C16/455

Abstract: A method for capping a copper surface on a substrate. In embodiments, the methods include exposing a substrate including a copper surface and a dielectric surface to a cobalt precursor gas and a process gas including a reducing agent to selectively form a first cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, wherein a flow rate ratio of process gas to cobalt precursor gas is at least 300:1.

公开(公告)号：US20190148150A1

公开(公告)日：2019-05-16

申请号：US16172786

申请日：2018-10-27

Applicant: Applied Materials, Inc.

Inventor： Joung Joo LEE ,  Feng CHEN ,  Zhiyuan WU ,  Atashi BASU ,  Mehul B. NAIK ,  Yufei HU

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/528

Abstract: Methods for forming a capping protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming capping protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal silicide layer on a metal line bounded by a dielectric bulk insulating layer in a back end interconnection structure formed on a substrate in a processing chamber; and forming a dielectric layer on the metal silicide layer.