公开(公告)号：US20240162007A1

公开(公告)日：2024-05-16

申请号：US17984772

申请日：2022-11-10

Applicant: Applied Materials, Inc.

Inventor： Deyang LI ,  Sunil SRINIVASAN ,  Yi-Chuan CHOU ,  Shahid RAUF ,  Kuan-Ting LIU ,  Jason A. KENNEY ,  Chung LIU ,  Olivier P. JOUBERT ,  Shreeram Jyoti DASH ,  Aaron EPPLER ,  Michael Thomas NICHOLS

IPC: H01J37/32

CPC classification number: H01J37/32174 ,  H01J37/32128 ,  H01J37/32146 ,  H01J2237/3341 ,  H01J2237/3346

Abstract: Embodiments of the present disclosure generally relate to a system used in a semiconductor device manufacturing process. More specifically, embodiments provided herein generally include apparatus and methods for synchronizing and controlling the delivery of an RF bias signal and a pulsed voltage waveform to one or more electrodes within a plasma processing chamber. The apparatus and methods disclosed herein can be useful to at least minimize or eliminate a microloading effect created while processing small dimension features that have differing densities across various regions of a substrate. The plasma processing methods and apparatus described herein are configured to improve the control of various characteristics of the generated plasma and control an ion energy distribution (IED) of the plasma generated ions that interact with a surface of a substrate during plasma processing. The ability to synchronize and control waveform characteristics of a voltage waveform bias established on a substrate during processing allows for an improved control of the generated plasma and process of forming, for example, high-aspect ratio features in the surface of the substrate by a reactive ion etching process. As a result, greater precision for plasma processing can be achieved, which is described herein in more detail.

公开(公告)号：US20160293420A1

公开(公告)日：2016-10-06

申请号：US15043183

申请日：2016-02-12

Applicant: Applied Materials, Inc.

Inventor： Dai-Wen TANG ,  Hui SUN ,  Chung LIU ,  Benjamin SCHWARZ

IPC: H01L21/033 ,  H01L21/32 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31122 ,  H01L21/32137 ,  Y10S438/947

Abstract: Embodiments herein provide apparatus and methods for performing an etching process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has having a first group of openings defined therebetween and etching the spacer layer disposed on the substrate while forming an oxidation layer on the spacer layer.

Abstract translation: 本文的实施例提供了用于在多个图案化工艺中对具有良好轮廓控制的间隔层进行蚀刻工艺的装置和方法。 在一个实施例中，用于在多次图案化工艺期间图案化间隔层的方法包括在设置在衬底上的图案化结构的外表面上共形形成间隔层，其中图案化结构具有限定在其间的第一组开口和蚀刻 所述间隔层设置在所述衬底上，同时在所述间隔层上形成氧化层。