公开(公告)号：US12217060B1

公开(公告)日：2025-02-04

申请号：US18176457

申请日：2023-02-28

Applicant: Apple Inc.

Inventor： Francesco Spadini ,  Skanda K. Srinivasa ,  Reena Panda ,  Brian T. Mokrzycki ,  Haoyan Jia ,  Zhaoxiang Jin

IPC: G06F9/30

Abstract: Techniques are disclosed that relate to executing pairs of instructions. A processor may include fusion detector circuitry configured to detect a pair of fetched instructions and fuse the pair of fetched instructions into a fused instruction operation, and execution circuitry coupled to the fusion detector circuitry and configured to execute the fused instruction operation. In some embodiments the pair of instructions is executable to generate a remainder of a division operation. In some embodiments the pair of instructions is executable to compare two operands and perform a write operation based on the comparison. In some embodiments the pair of instructions is executable to perform an operation and apply a mask bit sequence to the result. The fusion detector circuitry may also be configured to obtain first and second portions of a constant value from first and second instructions and store the first and second portions in a destination register.

公开(公告)号：US11900118B1

公开(公告)日：2024-02-13

申请号：US17817866

申请日：2022-08-05

Applicant: Apple Inc.

Inventor： John D. Pape ,  Francesco Spadini ,  Zhaoxiang Jin

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3814 ,  G06F9/30134 ,  G06F9/3826 ,  G06F9/3838

Abstract: An apparatus includes a rescue buffer circuit, a store queue circuit, and a control circuit. The rescue buffer circuit may be configured to retain address information related to store instructions. The store queue circuit may be configured to buffer dependency information related to a particular store instruction until the particular store instruction is released to be executed. The control circuit may be configured to cause a subset of the dependency information for the particular store instruction to be written to the rescue buffer circuit. The rescue buffer circuit may be configured to retain the subset after the dependency information has been released from the store queue circuit, and to perform a subsequent load instruction corresponding to a memory location associated with the particular store instruction using the subset of the dependency information from the rescue buffer circuit.