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公开(公告)号：US20240258924A1
公开(公告)日：2024-08-01
申请号：US18634182
申请日：2024-04-12
Applicant: Apple Inc.
Inventor： Sujan K. Manohar , Jay B. Fletcher
Abstract: In some embodiments, a power converter circuit included in a computer system magnetizes and de-magnetizes an inductor coupled to a switch node using high-side and low-side switches to alternatively couple a switch node to an input power supply node and a ground supply node. In response to detecting a drop in the voltage level of the input power supply node, the power converter circuit may adjust an on-resistance of the high-side switch to maintain performance at the lower voltage level of the input power supply node.
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公开(公告)号：US11287839B2
公开(公告)日：2022-03-29
申请号：US16583008
申请日：2019-09-25
Applicant: Apple Inc.
Inventor： Sujan K. Manohar , Jay B. Fletcher , Nathan F. Hanagami
Abstract: A dual loop LDO voltage regulator is disclosed. The voltage regulator circuit includes a first current mirror having first and second transistors having source terminals coupled to an input voltage node. The circuit further includes a second current mirror having third and fourth transistors, wherein drain terminals of the third and fourth transistors are coupled to drain terminals of the first and second transistors, respectively. A feedback circuit is coupled between source terminals of the third and fourth transistors, and is configured to generate a feedback signal based on a reference voltage and an output voltage present on the source terminal of the fourth transistor. The first and second current mirrors form a first control loop, and wherein the first and second current mirrors and the feedback circuit form a second control loop.
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公开(公告)号：US20220155808A1
公开(公告)日：2022-05-19
申请号：US16953257
申请日：2020-11-19
Applicant: Apple Inc.
Inventor： Sujan K. Manohar , Jay B. Fletcher
Abstract: A dropout detection circuit for an LDO voltage regulator is disclosed. An LDO voltage regulator includes a power transistor having a drain terminal coupled to an output voltage node and a gate terminal coupled to an output of an error amplifier. A source terminal of the power transistor is coupled to an input voltage node. The circuit further includes a detection circuit having a first input coupled to the gate terminal and a second input coupled to the drain terminal. The detection circuit is configured to generate an indication responsive to detecting that the LDO voltage regulator has entered operation below a minimum dropout.
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Patent Agency Ranking
公开(公告)号：US12244231B2
公开(公告)日：2025-03-04
申请号：US18634182
申请日：2024-04-12
Applicant: Apple Inc.
Inventor： Sujan K. Manohar , Jay B. Fletcher
Abstract: In some embodiments, a power converter circuit included in a computer system magnetizes and de-magnetizes an inductor coupled to a switch node using high-side and low-side switches to alternatively couple a switch node to an input power supply node and a ground supply node. In response to detecting a drop in the voltage level of the input power supply node, the power converter circuit may adjust an on-resistance of the high-side switch to maintain performance at the lower voltage level of the input power supply node.
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公开(公告)号：US12034370B2
公开(公告)日：2024-07-09
申请号：US17651173
申请日：2022-02-15
Applicant: Apple Inc.
Inventor： Sujan K. Manohar , Jay B. Fletcher
Abstract: A power converter circuit included in a computer system magnetizes and de-magnetizes an inductor coupled to a switch node using high-side and low-side switches to alternatively couple a switch node to an input power supply node and a ground supply node. In response to detecting a drop in the voltage level of the input power supply node, the power converter circuit may adjust an on-resistance of the high-side switch to maintain performance at the lower voltage level of the input power supply node.
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公开(公告)号：US20230261573A1
公开(公告)日：2023-08-17
申请号：US17651173
申请日：2022-02-15
Applicant: Apple Inc.
Inventor： Sujan K. Manohar , Jay B. Fletcher
Abstract: A power converter circuit included in a computer system magnetizes and demagnetizes an inductor coupled to a switch node using high-side and low-side switches to alternatively couple a switch node to an input power supply node and a ground supply node. In response to detecting a drop in the voltage level of the input power supply node, the power converter circuit may adjust an on-resistance of the high-side switch to maintain performance at the lower voltage level of the input power supply node.
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公开(公告)号：US20210089068A1
公开(公告)日：2021-03-25
申请号：US16583008
申请日：2019-09-25
Applicant: Apple Inc.
Inventor： Sujan K. Manohar , Jay B. Fletcher , Nathan F. Hanagami
Abstract: A dual loop LDO voltage regulator is disclosed. The voltage regulator circuit includes a first current mirror having first and second transistors having source terminals coupled to an input voltage node. The circuit further includes a second current mirror having third and fourth transistors, wherein drain terminals of the third and fourth transistors are coupled to drain terminals of the first and second transistors, respectively. A feedback circuit is coupled between source terminals of the third and fourth transistors, and is configured to generate a feedback signal based on a reference voltage and an output voltage present on the source terminal of the fourth transistor. The first and second current mirrors form a first control loop, and wherein the first and second current mirrors and the feedback circuit form a second control loop.
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公开(公告)号：US10812082B1
公开(公告)日：2020-10-20
申请号：US16586146
申请日：2019-09-27
Applicant: Apple Inc.
Inventor： Sujan K. Manohar , Nathan F. Hanagami
IPC: H03L5/00 , H03K19/0185 , H03K17/687 , H03K19/017
Abstract: A level shifter circuit included in a computer system may include bootstrap and feedback nodes. The level shifter circuit may discharge the feedback node in response to high-going transition on a received input signal generated using a first power supply signal. The level shifter circuit may also increase a voltage level of the bootstrap node in response to the high-going transition and charge the bootstrap node, in response to the discharge of the feedback node, to a voltage level of a second power supply signal that is different than a voltage level of the first power supply signal. The level shifter circuit may generate an output signal using the voltage levels of the feedback node and the second power supply signal.
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