公开(公告)号：US12118332B2

公开(公告)日：2024-10-15

申请号：US18045577

申请日：2022-10-11

Applicant: Apple Inc.

Inventor： Ali Sazegari ,  Segev Elmalem ,  O-Cheng Chang ,  Jingwei Zhang ,  Ido Soffair ,  Aaftab A. Munshi

IPC: G06F7/552

CPC classification number: G06F7/552

Abstract: Techniques are disclosed relating to dedicated power function circuitry for a floating-point power instruction. In some embodiments, execution circuitry is configured to execute a floating-point power instruction to evaluate the power function xy as 2y log2x. In some embodiments, base-2 logarithm circuitry is configured to evaluate a base-2 logarithm for a first input (e.g., log2 x) by determining coefficients for a polynomial function and evaluating the polynomial function using the determined coefficients and the first input. In some embodiments, multiplication circuitry multiplies the base-2 logarithm result by a second input to generate a multiplication result. In some embodiments, base-2 power function circuitry is configured to evaluate a base-2 power function for the multiplication result. Disclosed techniques may advantageously increase performance and reduce power consumption of floating-point power function operations with reasonable area and accuracy, relative to traditional techniques.

公开(公告)号：US20250053380A1

公开(公告)日：2025-02-13

申请号：US18825013

申请日：2024-09-05

Applicant: Apple Inc.

Inventor： Ali Sazegari, PhD ,  Segev Elmalem ,  O-Cheng Chang ,  Jingwei Zhang ,  Ido Soffair ,  Aaftab A. Munshi

IPC: G06F7/552

Abstract: Techniques are disclosed relating to dedicated power function circuitry for a floating-point power instruction. In some embodiments, execution circuitry is configured to execute a floating-point power instruction to evaluate the power function xy as 2y log2 x. In some embodiments, base-2 logarithm circuitry is configured to evaluate a base-2 logarithm for a first input (e.g., log2 x) by determining coefficients for a polynomial function and evaluating the polynomial function using the determined coefficients and the first input. In some embodiments, multiplication circuitry multiplies the base-2 logarithm result by a second input to generate a multiplication result. In some embodiments, base-2 power function circuitry is configured to evaluate a base-2 power function for the multiplication result. Disclosed techniques may advantageously increase performance and reduce power consumption of floating-point power function operations with reasonable area and accuracy, relative to traditional techniques.

公开(公告)号：US20240094989A1

公开(公告)日：2024-03-21

申请号：US18045577

申请日：2022-10-11

Applicant: Apple Inc.

Inventor： Ali Sazegari ,  Segev Elmalem ,  O-Cheng Chang ,  Jingwei Zhang ,  Ido Soffair ,  Aaftab A. Munshi

IPC: G06F7/487

CPC classification number: G06F7/4876

Abstract: Techniques are disclosed relating to dedicated power function circuitry for a floating-point power instruction. In some embodiments, execution circuitry is configured to execute a floating-point power instruction to evaluate the power function xy as 2y log2x. In some embodiments, base-2 logarithm circuitry is configured to evaluate a base-2 logarithm for a first input (e.g., log2 x) by determining coefficients for a polynomial function and evaluating the polynomial function using the determined coefficients and the first input. In some embodiments, multiplication circuitry multiplies the base-2 logarithm result by a second input to generate a multiplication result. In some embodiments, base-2 power function circuitry is configured to evaluate a base-2 power function for the multiplication result. Disclosed techniques may advantageously increase performance and reduce power consumption of floating-point power function operations with reasonable area and accuracy, relative to traditional techniques.