公开(公告)号：US09454486B2

公开(公告)日：2016-09-27

申请号：US13940525

申请日：2013-07-12

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Perumal R Subramoniam ,  Prashant Jain

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/1027 ,  G06F2212/6022 ,  G06F2212/654

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a pending request buffer and a control circuit. The pending request buffer may include a plurality of buffer entries. The control circuit may be coupled to the pending request buffer and may be configured to receive a request for a first cache line from a pre-fetch engine, and store the received request in an entry of the pending request buffer. The control circuit may be further configured to receive a request for a second cache line from a processor, and store the request received from the processor in the entry of the pending request buffer in response to a determination that the second cache line is the same as the first cache line.

Abstract translation: 公开了一种用于处理计算系统中的缓存请求的装置。 该装置可以包括未决请求缓冲器和控制电路。 待决请求缓冲器可以包括多个缓冲器条目。 控制电路可以耦合到未决请求缓冲器，并且可以被配置为从预取引擎接收对第一高速缓存行的请求，并将接收到的请求存储在待处理请求缓冲器的条目中。 控制电路还可以被配置成从处理器接收对第二高速缓存行的请求，并且响应于第二高速缓存行与第二高速缓存行的相同的确定，将从处理器接收的请求存储在待处理请求缓冲器的条目中 第一个缓存行。