公开(公告)号：US20170293470A1

公开(公告)日：2017-10-12

申请号：US15092401

申请日：2016-04-06

Applicant: Apple Inc.

Inventor： Liang-Kai Wang ,  Terence M. Potter ,  Andrew M. Havlir ,  Yu Sun ,  Nicolas X. Pena ,  Xiao-Long Wu ,  Christopher A. Burns

IPC: G06F7/483

CPC classification number: G06F7/483 ,  G06F7/5443

Abstract: Techniques are disclosed relating to floating-point operations with down-conversion. In some embodiments, a floating-point unit is configured to perform fused multiply-addition operations based on first and second different instruction types. In some embodiments, the first instruction type specifies result in the first floating-point format and the second instruction type specifies fused multiply addition of input operands in the first floating-point format to generate a result in a second, lower-precision floating-point format. For example, the first format may be a 32-bit format and the second format may be a 16-bit format. In some embodiments, the floating-point unit includes rounding circuitry, exponent circuitry, and/or increment circuitry configured to generate signals for the second instruction type in the same pipeline stage as for the first instruction type. In some embodiments, disclosed techniques may reduce the number of pipeline stages included in the floating-point circuitry.

公开(公告)号：US10282169B2

公开(公告)日：2019-05-07

申请号：US15092401

申请日：2016-04-06

Applicant: Apple Inc.

Inventor： Liang-Kai Wang ,  Terence M. Potter ,  Andrew M. Havlir ,  Yu Sun ,  Nicolas X. Pena ,  Xiao-Long Wu ,  Christopher A. Burns

IPC: G06F7/483 ,  G06F7/544

Abstract: Techniques are disclosed relating to floating-point operations with down-conversion. In some embodiments, a floating-point unit is configured to perform fused multiply-addition operations based on first and second different instruction types. In some embodiments, the first instruction type specifies result in the first floating-point format and the second instruction type specifies fused multiply addition of input operands in the first floating-point format to generate a result in a second, lower-precision floating-point format. For example, the first format may be a 32-bit format and the second format may be a 16-bit format. In some embodiments, the floating-point unit includes rounding circuitry, exponent circuitry, and/or increment circuitry configured to generate signals for the second instruction type in the same pipeline stage as for the first instruction type. In some embodiments, disclosed techniques may reduce the number of pipeline stages included in the floating-point circuitry.