公开(公告)号：US10089077B1

公开(公告)日：2018-10-02

申请号：US15402820

申请日：2017-01-10

Applicant: Apple Inc.

Inventor： Liang-Kai Wang ,  Terence M. Potter ,  Brian K. Reynolds ,  Justin Friesenhahn

IPC: G06F7/50 ,  G06F7/505

Abstract: Techniques are disclosed relating to performing arithmetic operations to generate values for different related threads. In some embodiments, the threads are graphics threads and the values are operand locations. In some embodiments, an apparatus performs an arithmetic operation using first circuitry, on type value inputs for different threads that are encoded to represent values to be operated on by the first circuitry. In some embodiments, second arithmetic circuitry is configured to perform an arithmetic operation on an output of the first circuitry and an input (e.g., address information such as a base and an offset) that is common to the different threads and has a greater number of bits than the output of the first circuitry. In various embodiments, disclosed techniques may allow decoding of encoded values for different threads (which may reduce memory requirements relative to non-encoded values) with a shorter critical path and lower power consumption, e.g., relative to sequential decoding.

公开(公告)号：US20190034166A1

公开(公告)日：2019-01-31

申请号：US16146147

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： Liang-Kai Wang ,  Terence M. Potter ,  Brian K. Reynolds ,  Justin Friesenhahn

IPC: G06F7/505

CPC classification number: G06F7/505 ,  G06F9/30 ,  G06T9/00

Abstract: Techniques are disclosed relating to performing arithmetic operations to generate values for different related threads. In some embodiments, the threads are graphics threads and the values are operand locations. In some embodiments, an apparatus includes circuitry configured to generate results for multiple threads by performing a plurality of arithmetic operations indicated by an instruction. In some embodiments, the instruction specifies: an input value that is common to the multiple threads and, for at least one of the multiple threads, a type value that indicates whether to generate a result for the thread by performing an arithmetic operation based on a first input that is a result of an arithmetic operation from another thread of the multiple threads or to generate a result for the thread using the input value that is common to the multiple threads. In some embodiments, the circuitry is configured to generate a result for the at least one of the multiple threads by selectively performing the arithmetic operation or using the input value that is common to the multiple threads based on the type value.

公开(公告)号：US12164927B2

公开(公告)日：2024-12-10

申请号：US18054380

申请日：2022-11-10

Applicant: Apple Inc.

Inventor： Justin Friesenhahn ,  Benjiman L. Goodman

IPC: G06F9/38

Abstract: Techniques are disclosed relating to instruction scheduling in the context of instruction cache misses. In some embodiments, first-stage scheduler circuitry is configured to assign threads to channels and second-stage scheduler circuitry is configured to assign an operation from a given channel to a given execution pipeline based on decode of an operation for that channel. In some embodiments, thread replacement circuitry is configured to, in response to an instruction cache miss for an operation of a first thread assigned to a first channel, deactivate the first thread from the first channel.

公开(公告)号：US20240095031A1

公开(公告)日：2024-03-21

申请号：US18054380

申请日：2022-11-10

Applicant: Apple Inc.

Inventor： Justin Friesenhahn ,  Benjiman L. Goodman

IPC: G06F9/30

CPC classification number: G06F9/30079 ,  G06F9/30047 ,  G06F9/3009 ,  G06F9/30145

Abstract: Techniques are disclosed relating to instruction scheduling in the context of instruction cache misses. In some embodiments, first-stage scheduler circuitry is configured to assign threads to channels and second-stage scheduler circuitry is configured to assign an operation from a given channel to a given execution pipeline based on decode of an operation for that channel. In some embodiments, thread replacement circuitry is configured to, in response to an instruction cache miss for an operation of a first thread assigned to a first channel, deactivate the first thread from the first channel.

公开(公告)号：US10387119B2

公开(公告)日：2019-08-20

申请号：US16146147

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： Liang-Kai Wang ,  Terence M. Potter ,  Brian K. Reynolds ,  Justin Friesenhahn

IPC: G06F7/505 ,  G06F9/30 ,  G06T9/00

Abstract: Techniques are disclosed relating to performing arithmetic operations to generate values for different related threads. In some embodiments, the threads are graphics threads and the values are operand locations. In some embodiments, an apparatus includes circuitry configured to generate results for multiple threads by performing a plurality of arithmetic operations indicated by an instruction. In some embodiments, the instruction specifies: an input value that is common to the multiple threads and, for at least one of the multiple threads, a type value that indicates whether to generate a result for the thread by performing an arithmetic operation based on a first input that is a result of an arithmetic operation from another thread of the multiple threads or to generate a result for the thread using the input value that is common to the multiple threads. In some embodiments, the circuitry is configured to generate a result for the at least one of the multiple threads by selectively performing the arithmetic operation or using the input value that is common to the multiple threads based on the type value.