公开(公告)号：US20250094355A1

公开(公告)日：2025-03-20

申请号：US18544110

申请日：2023-12-18

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  Brian T. Mokrzycki ,  Jonathan Y. Tong ,  Michael D. Snyder ,  James N. Hardage

IPC: G06F12/1027

Abstract: Techniques are disclosed relating to using an instruction (e.g., a pre-translate instruction) to lock translations in TLB entries. The execution of the instruction may include storing translation information in a TLB entry, and setting an indication that the entry is locked. The processor circuitry may receive an invalidate command corresponding to the locked entry. Processor circuitry may, in response to the invalidate command and based on the indication that the entry is locked, maintain the locked entry in a valid state in the translation lookaside buffer circuitry, notwithstanding the invalidate command. Processor circuitry may be further configured to modify previously-stored data in a given entry to aggregate, in the entry, translation information for multiple regions of the second address space.

公开(公告)号：US20190220417A1

公开(公告)日：2019-07-18

申请号：US15874624

申请日：2018-01-18

Applicant: Apple Inc.

Inventor： David J. Williamson ,  Deepak Limaye ,  James N. Hardage

IPC: G06F12/12 ,  G06F9/46 ,  G06F8/41 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F12/12 ,  G06F8/433 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/461

Abstract: In an embodiment, a processor may include a register file including one or more sets of registers for one or more data types specified by the ISA implemented by the processor. The processor may have a processor mode in which the context is reduced, as compared to the full context. For example, for at least one of the data types, the registers included in the reduced context exclude one or more of the registers defined in the ISA for that data type. In an embodiment, one half or more of the registers for the data type may be excluded. When the processor is operating in a reduced context mode, the processor may detect instructions that use excluded registers, and may signal an exception for such instructions to prevent use of the excluded registers.