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公开(公告)号：US12199621B2
公开(公告)日：2025-01-14
申请号：US18135343
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Hideya Oshima , Reetika K Agarwal
Abstract: In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.
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公开(公告)号：US20240348254A1
公开(公告)日：2024-10-17
申请号：US18135343
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Hideya Oshima , Reetika K Agarwal
CPC classification number: H03L7/0893 , H02M3/07
Abstract: In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.
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