Bandwidth Control in PLL-Based Power Converter

    公开(公告)号:US20240106328A1

    公开(公告)日:2024-03-28

    申请号:US17934398

    申请日:2022-09-22

    Applicant: Apple Inc.

    CPC classification number: H02M3/158 H02M1/0009 H03L7/0891

    Abstract: A phase-locked loop (PLL)-based power converter is disclosed. A power converter includes a switch circuit having a switch node coupled to a regulated power supply node via an inductor and configured to source a supply current to the regulated power supply node using one or more control signals. A control circuit performs a phase-frequency comparison of a reference clock signal and a switching frequency of the switch circuit and generate a control voltage using results of the phase-frequency comparison. The control circuit further generates a control current using the control voltage, a voltage of the regulated power supply node, and a duty cycle of the switch circuit, and a demand current using the voltage level of the regulated power supply node and a reference voltage. Using the demand current, the control current, and a sensed version of the supply current, the control circuit generates the one or more control signals.

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