公开(公告)号：US12159142B1

公开(公告)日：2024-12-03

申请号：US18310919

申请日：2023-05-02

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Chang Xu ,  Deepankar Duggal ,  Debasish Chandra

IPC: G06F9/30 ,  G06F9/38

Abstract: Techniques are disclosed relating to predicting values for load operations. In some embodiments, front-end circuitry is configured to predict values of load operations based on multiple value tagged geometric length predictor (VTAGE) prediction tables (based on program counter information and branch history information). Training circuitry may adjust multiple VTAGE learning tables based on completed load operations. Control circuitry may pre-compute access information (e.g., an index) for a VTAGE learning table for a load based on branch history information that is available to the front-end circuitry but that is unavailable to the training circuitry, store the pre-computed access information, and provide the pre-computed access information from the first storage circuitry to the training circuitry to access the VTAGE learning table based on completion of the load. This may facilitate VTAGE training without pipelining the branch history information.

公开(公告)号：US20240329990A1

公开(公告)日：2024-10-03

申请号：US18740430

申请日：2024-06-11

Applicant: Apple Inc.

Inventor： Deepankar Duggal ,  Kulin N Kothari ,  Mridul Agarwal ,  Chang Xu ,  Yanran Yang ,  Richard F Russo ,  Yuan C Chou ,  Douglas C Holman

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/30087 ,  G06F9/3802 ,  G06F9/522

Abstract: A system, e.g., a system on a chip (SOC), may include one or more processors. A processor may execute an instruction synchronization barrier (ISB) instruction to enforce an ordering constraint on instructions. To execute the ISB instruction, the processor may determine whether contexts of the processor required for execution of instructions older than the ISB instruction are consumed for the older instructions. Responsive to determining that the contexts are consumed for the older instructions, the processor may initiate fetching of an instruction younger than the ISB instruction, without waiting for the older instructions to retire.

公开(公告)号：US12045615B1

公开(公告)日：2024-07-23

申请号：US17933040

申请日：2022-09-16

Applicant: Apple Inc.

Inventor： Deepankar Duggal ,  Kulin N Kothari ,  Mridul Agarwal ,  Chang Xu ,  Yanran Yang ,  Richard F Russo ,  Yuan C Chou ,  Douglas C Holman

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/30087 ,  G06F9/3802 ,  G06F9/522

Abstract: A system, e.g., a system on a chip (SOC), may include one or more processors. A processor may execute an instruction synchronization barrier (ISB) instruction to enforce an ordering constraint on instructions. To execute the ISB instruction, the processor may determine whether contexts of the processor required for execution of instructions older than the ISB instruction are consumed for the older instructions. Responsive to determining that the contexts are consumed for the older instructions, the processor may initiate fetching of an instruction younger than the ISB instruction, without waiting for the older instructions to retire.