公开(公告)号：US11966750B2

公开(公告)日：2024-04-23

申请号：US17809891

申请日：2022-06-29

申请人： Ampere Computing LLC

发明人： Shivnandan Kaushik ,  Harb Abdulhamid ,  Vanshidhar Konda ,  Yogesh Bansal ,  Sachhidh Kannan ,  Sebastien Hily

IPC分类号： G06F9/4401 ,  G06F9/48 ,  G06F15/173

CPC分类号： G06F9/4403 ,  G06F9/4812 ,  G06F15/17381

摘要： Disclosed are techniques for management of multiple processor cores in a multi-core system-on-chip (SoC). In an implementation, the SoC may configure each processor core in a first subset of processor cores as a management controller for performing system management functions for processor cores not in the first subset, the first subset comprising at least one processor core from the plurality of processor cores. System management functions are handled by the processor cores in the first subset, while operating system functions are handled by the processor cores not in the first subset. In an implementation, the number of processor cores to be included in the first subset (which may be zero if it is desired that the SoC may operate in legacy mode), may be controlled at boot time according to a boot setting.

公开(公告)号：US11977638B2

公开(公告)日：2024-05-07

申请号：US17809888

申请日：2022-06-29

申请人： Ampere Computing LLC

发明人： Sachhidh Kannan ,  Shivnandan Kaushik ,  Harb Abdulhamid ,  Yogesh Bansal ,  Vanshidhar Konda

IPC分类号： G06F21/57 ,  G06F8/65 ,  G06F8/656

CPC分类号： G06F21/572 ,  G06F8/65 ,  G06F8/656

摘要： Disclosed are techniques for performing a low-impact firmware update to a first microcontroller. In an aspect, a security entity communicatively coupled to the first microcontroller receives an update to firmware of the first microcontroller, authenticates the update to the firmware of the first microcontroller to prevent a security-related rollback, offloads system management tasks and interrupt handling from the first microcontroller to at least a second microcontroller communicatively coupled to the first microcontroller, coordinates installation of the update to the firmware of the first microcontroller without taking processing cycles from host software, and restores, to the first microcontroller, system management states occurring after the system management tasks and interrupt handling are offloaded from the first microcontroller.