公开(公告)号：US07573884B2

公开(公告)日：2009-08-11

申请号：US11681784

申请日：2007-03-04

申请人： Amos Klimker ,  Liran Brecher ,  Etai Zaltsman

发明人： Amos Klimker ,  Liran Brecher ,  Etai Zaltsman

IPC分类号： H04L12/54 ,  H04L12/56

CPC分类号： H04L12/2801 ,  H04L45/00 ,  H04L45/245 ,  H04L47/10 ,  H04L47/125 ,  H04L47/34

摘要： A novel apparatus and method of packet re-sequencing applicable to systems wherein packets are assigned sequence numbers and transmitted over multiple channels with the requirement they be re-ordered at the receiving side. The mechanism is particularly suitable for use in cable systems adapted to implement the DOCSIS 3.0 specification which permits the bonding of a plurality of downstream channels into a single virtual high data rate pipe. In operation, received packets are stored in a memory whereby a pointer to the memory storage location is written into a context table diagram in accordance with the sequence number extracted from the packet. Packets are released in sequence order regardless of the order in which they were received.

摘要翻译： 一种分组重新排序的新颖的装置和方法，适用于其中分组被分配序列号并且在多个信道上发送并且在接收侧被重新排序的要求的系统。 该机构特别适用于适用于实施DOCSIS 3.0规范的电缆系统，该规范允许将多个下游信道绑定到单个虚拟高数据速率管道中。 在操作中，接收的分组被存储在存储器中，由此根据从分组提取的序列号，将指向存储器存储位置的指针写入上下文表图。 数据包按照顺序排列，无论其接收顺序如何。

公开(公告)号：US20070206600A1

公开(公告)日：2007-09-06

申请号：US11681784

申请日：2007-03-04

申请人： Amos Klimker ,  Liran Brecher ,  Etai Zaltsman

发明人： Amos Klimker ,  Liran Brecher ,  Etai Zaltsman

IPC分类号： H04L12/54 ,  H04L12/56

CPC分类号： H04L12/2801 ,  H04L45/00 ,  H04L45/245 ,  H04L47/10 ,  H04L47/125 ,  H04L47/34

摘要： A novel apparatus and method of packet re-sequencing applicable to systems wherein packets are assigned sequence numbers and transmitted over multiple channels with the requirement they be re-ordered at the receiving side. The mechanism is particularly suitable for use in cable systems adapted to implement the DOCSIS 3.0 specification which permits the bonding of a plurality of downstream channels into a single virtual high data rate pipe. In operation, received packets are stored in a memory whereby a pointer to the memory storage location is written into a context table diagram in accordance with the sequence number extracted from the packet. Packets are released in sequence order regardless of the order in which they were received.

摘要翻译： 一种分组重新排序的新颖的装置和方法，适用于其中分组被分配序列号并且在多个信道上发送并且在接收侧被重新排序的要求的系统。 该机构特别适用于适用于实施DOCSIS 3.0规范的电缆系统，该规范允许将多个下游信道绑定到单个虚拟高数据速率管道中。 在操作中，接收的分组被存储在存储器中，由此根据从分组提取的序列号，将指向存储器存储位置的指针写入上下文表图。 数据包按照顺序排列，无论其接收顺序如何。

公开(公告)号：US20190034351A1

公开(公告)日：2019-01-31

申请号：US15826105

申请日：2017-11-29

申请人： Barak Hermesh ,  Ziv Kfir ,  Amos Klimker ,  Doron Nakar ,  Lior Nevo

发明人： Barak Hermesh ,  Ziv Kfir ,  Amos Klimker ,  Doron Nakar ,  Lior Nevo

IPC分类号： G06F12/123 ,  G06F9/38 ,  G06F9/50 ,  G06F12/0862

摘要： Various systems and methods for queue management in computer memory are described herein. A system for implementing a zero thrash cache queue manager includes a processor subsystem to: receive a memory access request for a queue; write data to a queue tail cache line in a cache when the memory access request is to add data to the queue, the queue tail cache line protected from being evicted from the cache; and read data from a current queue head cache line in the cache when the memory access request is to remove data from the queue, the current queue head cache line protected from being evicted from the cache.

公开(公告)号：US20130343501A1

公开(公告)日：2013-12-26

申请号：US13529366

申请日：2012-06-21

申请人： Bernard Arambepola ,  Shaul Shulman ,  Naor Goldman ,  Amos Klimker ,  Noam Tal

发明人： Bernard Arambepola ,  Shaul Shulman ,  Naor Goldman ,  Amos Klimker ,  Noam Tal

IPC分类号： H04L7/00

CPC分类号： H04N21/6118 ,  H04L25/14 ,  H04L27/34 ,  H04N21/4382 ,  H04N21/4385 ,  H04N21/4622 ,  H04N21/631

摘要： A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to many up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.

摘要翻译： 描述了一种系统和方法来提供基于DOCSIS标准的下一代电缆网关/调制解调器，其具有同步组合物理层中的信道以增加用于同轴电缆数据传输的总比特率的方案。 系统和方法将发射机处的与多个通道相关联的计数器（包括连续性计数器）同步到零，然后允许各个通道上的计数器单独增加。 在接收机处，基于与每个信道相关联的计数器提供的信息，各个信道的各个信道延迟将因此被识别。 接收器处的缓冲器被通知并用于将多个通道中的一个或多个单独地延迟到许多向上的连续性计数器值。 以这种方式，缓冲器用于基本上均衡各个信道中的延迟，连续性计数器表示用于指定单独信道的各个延迟的机制。

公开(公告)号：US08781052B2

公开(公告)日：2014-07-15

申请号：US13529366

申请日：2012-06-21

申请人： Bernard Arambepola ,  Shaul Shulman ,  Naor Goldman ,  Amos Klimker ,  Noam Tal

发明人： Bernard Arambepola ,  Shaul Shulman ,  Naor Goldman ,  Amos Klimker ,  Noam Tal

IPC分类号： H04J3/06 ,  H04L7/04 ,  H04L7/00

CPC分类号： H04N21/6118 ,  H04L25/14 ,  H04L27/34 ,  H04N21/4382 ,  H04N21/4385 ,  H04N21/4622 ,  H04N21/631

摘要： A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to marry up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.

摘要翻译： 描述了一种系统和方法来提供基于DOCSIS标准的下一代电缆网关/调制解调器，其具有同步组合物理层中的信道以增加用于同轴电缆数据传输的总比特率的方案。 系统和方法将发射机处的与多个通道相关联的计数器（包括连续性计数器）同步到零，然后允许各个通道上的计数器单独增加。 在接收机处，基于与每个信道相关联的计数器提供的信息，各个信道的各个信道延迟将因此被识别。 接收器处的缓冲器被通知并用于单独延迟多个通道中的一个或多个以结束连续性计数器值。 以这种方式，缓冲器用于基本上均衡各个信道中的延迟，连续性计数器表示用于指定单独信道的各个延迟的机制。