公开(公告)号：US08406258B1

公开(公告)日：2013-03-26

申请号：US12752984

申请日：2010-04-01

Applicant: Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

Inventor： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

IPC: H04J3/06

CPC classification number: H03M9/00 ,  H03K19/1776 ,  H04J3/047 ,  H04J3/0685

Abstract: One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。 每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。 第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号 基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。 时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。 还公开了其它实施例和特征。

公开(公告)号：US08299802B2

公开(公告)日：2012-10-30

申请号：US12263290

申请日：2008-10-31

Applicant: Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

Inventor： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

IPC: G01R31/02

CPC classification number: G01R31/3167

Abstract: An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

Abstract translation: 提出了一种能够监视模拟模块内的模拟电压的集成电路。 集成电路具有模拟测试复用器（多路复用器），其输入端连接到模拟模块内的感兴趣的模拟电压。 模拟测试复用器将选定的模拟电压从模拟模块引导到模拟测试复用器的输出。 集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。 集成电路还包括用于将来自模拟测试多路复用器的所选模拟电压转换为数字表示的模数转换器。

公开(公告)号：US08184651B2

公开(公告)日：2012-05-22

申请号：US12100360

申请日：2008-04-09

Applicant: Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

Inventor： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

IPC: H04L12/56

CPC classification number: H04L49/30 ,  H04L49/352

Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10 GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

Abstract translation: 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。 该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

公开(公告)号：US07834712B2

公开(公告)日：2010-11-16

申请号：US12277810

申请日：2008-11-25

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

IPC: H03B5/00

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

Abstract: An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

Abstract translation: 振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。 振荡器电路还包括第二导电层中的变容二极管，电容器和选项导体。 选项导体形成晶体管之一和电容器或变容二极管之间的连接的至少一部分。

公开(公告)号：US08290750B1

公开(公告)日：2012-10-16

申请号：US13036437

申请日：2011-02-28

Applicant: Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

Inventor： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

IPC: H03F1/26

CPC classification number: H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

Abstract: Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

Abstract translation: 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

公开(公告)号：US07602212B1

公开(公告)日：2009-10-13

申请号：US11904003

申请日：2007-09-24

Applicant: Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

Inventor： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

IPC: G06F7/38 ,  H03K19/173

CPC classification number: H03K19/17736 ,  H03K19/17732 ,  H03K19/17744

Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes high-speed serial data signal interface channels, some of which include more circuitry that is dedicated to performing various high-speed serial interface functions than others of those channels have. To increase the flexibility with which such circuitry in a more feature-rich channel can be used, routing is provided for selectively allowing a less feature-rich channel to use certain dedicated circuitry of a more feature-rich channel that is not itself using all of its dedicated circuitry.

Abstract translation: 集成电路（例如，可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括高速串行数据信号接口通道，其中一些包括更多专用于执行各种高速串行数据 接口功能比其他那些通道有。 为了增加可以使用更多功能丰富的信道中的这种电路的灵活性，提供路由选择性地允许较不富有特征的信道使用更多功能丰富的信道的某些专用电路，其不是本身使用全部 其专用电路。

公开(公告)号：US20090154591A1

公开(公告)日：2009-06-18

申请号：US12002540

申请日：2007-12-17

Applicant: Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Weiqi Ding

Inventor： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Weiqi Ding

IPC: H04L27/00

CPC classification number: H04L25/028

Abstract: Transmitter driver circuitry for outputting a high-speed serial data signal (e.g., in the range of about 10 gigabits per second or higher) includes H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor in the H-tree driver circuitry is constructed and connected to provide electrostatic discharge protection. PMOS and NMOS current sources are used for the H-tree driver circuitry to enhance power supply noise rejection.

Abstract translation: 用于输出高速串行数据信号（例如，在大约10吉比特每秒或更高的范围内）的发射器驱动器电路包括仅具有主驱动器级和抽头后驱动级的H树驱动器电路。 H树驱动器电路中的至少一个晶体管被构造和连接以提供静电放电保护。 PMOS和NMOS电流源用于H-tree驱动器电路，以增强电源噪声抑制。

公开(公告)号：US08831140B2

公开(公告)日：2014-09-09

申请号：US11687052

申请日：2007-03-16

Applicant: Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

Inventor： Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

IPC: H04L27/00 ,  H03K19/177 ,  G06F13/38 ,  H04L5/14

CPC classification number: G06F13/385 ,  H03K19/177 ,  H03K19/17744 ,  H04L5/1446

Abstract: Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from “0” to “1” to “0” or from “1” to “0” to “1”) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating in full-rate mode. The rate negotiation logic may share a phase detector with clock data recovery circuitry in the interface. The phase detector may be a bang-bang phase detector specially adapted to detect single-bit transitions.

Abstract translation: 用于可编程逻辑器件中的高速串行接口的自动速率协商逻辑确定单个位转换的多次出现（即，从“0”到“1”到“0”或从“1”到“1”的数据转换 0“到”1“）发生在高速串行接口的数据信道上的预定时间间隔内。 间隔优选地被选择为使得多次出现单位转换意味着数据信道以全速率模式运行。 速率协商逻辑可以在接口中共享具有时钟数据恢复电路的相位检测器。 相位检测器可以是专门用于检测单位转换的爆发相位检测器。

公开(公告)号：US08669828B1

公开(公告)日：2014-03-11

申请号：US12909739

申请日：2010-10-21

Applicant: Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

Inventor： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

IPC: H04B3/28

CPC classification number: H01L23/642 ,  H01L2924/0002 ,  H05K1/0231 ,  H01L2924/00

Abstract: Integrated circuits with decoupling capacitor circuitry are provided. Decoupling capacitor circuitry may include multiple arrays of decoupling capacitors. Each decoupling capacitor array may have a corresponding decoupling capacitor monitoring circuit that is associated with that decoupling capacitor array. Each decoupling capacitor monitoring circuit may include a resistor and switching circuitry. Each decoupling capacitor monitoring circuit may be coupled to a comparator and control circuitry. During testing, the control circuitry may configure each decoupling capacitor array for leakage current testing one at a time. If a decoupling capacitor array is determined to exhibit excessive leakage currents, that decoupling capacitor array will be marked as defective and will be disabled from use. If the decoupling capacitor array is determined to exhibit tolerable leakage currents, that decoupling capacitor array will be enable for use to help reduce power supply noise.

Abstract translation: 提供具有去耦电容电路的集成电路。 去耦电容器电路可以包括多个去耦电容器阵列。 每个去耦电容器阵列可以具有与该去耦电容器阵列相关联的相应的去耦电容器监控电路。 每个去耦电容器监控电路可以包括电阻器和开关电路。 每个去耦电容器监控电路可以耦合到比较器和控制电路。 在测试期间，控制电路可以配置每个去耦电容器阵列以便一次一个地进行漏电流测试。 如果解耦电容器阵列被确定为表现出过多的漏电流，则该去耦电容阵列将被标记为有缺陷的并且将被禁止使用。 如果解耦电容器阵列被确定为表现出可容忍的漏电流，则该去耦电容器阵列将被用于帮助减少电源噪声。

公开(公告)号：US08175143B1

公开(公告)日：2012-05-08

申请号：US12037284

申请日：2008-02-26

Applicant: Wilson Wong ,  Tin H. Lai ,  Allen Chan ,  Tim Tri Hoang ,  Sergey Shumarayev

Inventor： Wilson Wong ,  Tin H. Lai ,  Allen Chan ,  Tim Tri Hoang ,  Sergey Shumarayev

IPC: H03H7/30

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03745 ,  H04L2025/03783

Abstract: A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.

Abstract translation: 用于在自适应均衡中选择正确的均衡曲线的方法和电路使用反馈回路，其中输入的高速串行数据被数字化和反序列化以用于设备的其余部分，并且还被自适应状态机 以提取用于数字化的参考电平并控制均衡曲线。 参考电平的检测和均衡曲线的选择可以以不同的速率进行，以避免彼此干扰。 状态机优选是可编程的。 这在任何设备中是有用的，但是特别适用于诸如PLD或其他可编程集成电路设备的可编程设备，其中条件可以根据用户逻辑设计而变化。