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    Logic simulation and/or emulation which follows hardware semantics
    1.
    发明授权
    Logic simulation and/or emulation which follows hardware semantics 有权

    公开(公告)号：US10423740B2

    公开(公告)日：2019-09-24

    申请号：US12432017

    申请日：2009-04-29

    Applicant: Alexander Rabinovitch ,  Ramesh Narayanaswamy

    Inventor： Alexander Rabinovitch ,  Ramesh Narayanaswamy

    IPC: G06F17/50

    Abstract: Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation.

    LOGIC SIMULATION AND/OR EMULATION WHICH FOLLOWS HARDWARE SEMANTICS
    2.
    发明申请
    LOGIC SIMULATION AND/OR EMULATION WHICH FOLLOWS HARDWARE SEMANTICS 审中-公开
    跟踪硬件语义的逻辑仿真和/或仿真

    公开(公告)号：US20100280814A1

    公开(公告)日：2010-11-04

    申请号：US12432017

    申请日：2009-04-29

    Applicant: Alexander Rabinovitch ,  Ramesh Narayanaswamy

    Inventor： Alexander Rabinovitch ,  Ramesh Narayanaswamy

    IPC: G06F17/50

    Abstract: Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation.

    Abstract translation: 本发明的一些实施例提供了用于模拟电路设计的技术和系统，使得仿真遵循硬件语义。 具体地，一些实施例确保仿真遵循硬件语义，通过适当地处理可能在逻辑模拟期间发生的时钟树中的状态元素和/或毛刺中的竞争条件。 每个逻辑模拟循环可以包括两个阶段：系统评估不依赖于时钟信号的电路设计的信号值的刺激应用阶段以及系统评估依赖于时钟的信号值的时钟传播阶段 信号。 本发明的一些实施例在刺激应用阶段期间采样信号值，并且在时钟传播阶段期间使用采样信号值来处理可能在逻辑模拟期间发生的时钟树中的状态元件和/或毛刺中的竞争条件。

    Tracing different states reached by a signal in a functional verification system
    3.
    发明授权
    Tracing different states reached by a signal in a functional verification system 有权
    跟踪功能验证系统中信号达到的不同状态

    公开(公告)号：US06470480B2

    公开(公告)日：2002-10-22

    申请号：US09738263

    申请日：2000-12-14

    Applicant: Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    Inventor： Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    IPC: G06F1750

    CPC classification number: G06F17/5022

    Abstract: A functional verification system which provides information as to whether a signal has reached all possible states. For example, in the case of a signal with 0 and 1 as possible states, a 2 bit variable is initialized to 00. When a value of 1 is received for the signal, the first bit is set to 1 and when a value of 0 is received for the signal, the second bit is set to 1. Accordingly, by examining the two bits, one may determine whether the signal has attained one or both of 0 and 1 states.

    Abstract translation: 提供关于信号是否已经达到所有可能状态的信息的功能验证系统。 例如，在0和1作为可能状态的信号的情况下，2位变量被初始化为00.当为该信号接收到1的值时，第一位被设置为1，当值为0 被接收到信号，第二位被设置为1.因此，通过检查两个比特，可以确定信号是否已经达到0和1状态中的一个或两个。

    Tracing the change of state of a signal in a functional verification system
    4.
    发明授权
    Tracing the change of state of a signal in a functional verification system 失效

    公开(公告)号：US06629297B2

    公开(公告)日：2003-09-30

    申请号：US09738259

    申请日：2000-12-14

    Applicant: Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    Inventor： Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    IPC: G06F1750

    CPC classification number: G06F17/5022

    Abstract: Functional verification system enabling the state of difference signals to be traced. The signals represent the outputs resulting from the evaluation of combinatorial blocks and/or a plurality of state elements forming a target design. The combinatorial blocks and/or a plurality of state elements may be grouped into multiple clusters, with each cluster being identified by a cluster identifier. The tracing circuit may include a mask memory, a previous state memory, and trace controller. Each of the mask memory and the previous state memory may contain a number of locations equal to the number of clusters such that the relevant mask and previous state information may be accessed based on the cluster identifier. The trace controller receives evaluated outputs for a cluster at bit positions specified by a corresponding mask. The trace controller compares the received bits with the previous values, and generates an entry in a trace buffer to record any changes.

    Functional verification of both cycle-based and non-cycle based designs
    6.
    发明授权
    Functional verification of both cycle-based and non-cycle based designs 有权
    基于循环和非循环的设计的功能验证

    公开(公告)号：US06480988B2

    公开(公告)日：2002-11-12

    申请号：US09738273

    申请日：2000-12-14

    Applicant: Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    Inventor： Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    IPC: G06F1750

    CPC classification number: G06F17/5022

    Abstract: A functional verification system which can be used to evaluate either cycle based designs or non-cycle based designs. A target design is partitioned into multiple clusters, with a combinatorial block in each cluster being assigned to an evaluation unit. A flow control memory stores data indicating the sequence in which the clusters are to be evaluated. The evaluation units evaluate combinatorial blocks within a cluster in parallel. A cluster control memory indicates the manner in which a register is to be modified upon the evaluation (and results) of each cluster. The instructions in the flow control memory may be designed to examine the contents of the register and evaluate the clusters in different sequences depending on the content of the register. Evaluation of a loop of a non-cycle based design can thus be terminated based on the contents of the register.

    Abstract translation: 功能验证系统，可用于评估基于循环的设计或基于非循环的设计。 目标设计被划分成多个群集，每个群集中的组合块被分配给一个评估单元。 流控制存储器存储指示要评估集群的序列的数据。 评估单元并行评估集群内的组合块。 集群控制存储器指示在每个集群的评估（和结果）上要修改寄存器的方式。 可以将流控制存储器中的指令设计成检查寄存器的内容，并根据寄存器的内容以不同的顺序对簇进行评估。 因此，可以基于寄存器的内容终止对基于非循环的设计的循环的评估。

    Run-time controller in a functional verification system
    9.
    发明授权
    Run-time controller in a functional verification system 失效

    公开(公告)号：US06625786B2

    公开(公告)日：2003-09-23

    申请号：US09738272

    申请日：2000-12-14

    Applicant: Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    Inventor： Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    IPC: G06F945

    CPC classification number: G06F17/5022

    Abstract: A run time controller which controls the sequence of evaluations of combinatorial blocks in a functional verification system. A target design is partitioned into multiple clusters, with each cluster in turn containing multiple combinatorial blocks. Evaluation units may be designed to evaluate the combinatorial blocks in each cluster in parallel. The run time controller may contain a flow processor, a flow control memory, and a cluster control memory. The contents of cluster control memory may be configured to specify how different condition bits/registers are to be altered upon evaluation of each cluster. The flow control memory is configured with instructions to data from different sources to be sent the evaluation units. In addition, the instructions are designed to examine the status of different registers and cause the flow processor to alter the evaluation flows.

    Method for delay immune and accelerated evaluation of digital circuits by compiling asynchronous completion handshaking means
    10.
    发明授权
    Method for delay immune and accelerated evaluation of digital circuits by compiling asynchronous completion handshaking means 有权
    通过编译异步完成握手手段来延迟免疫和加速评估数字电路的方法

    公开(公告)号：US08359186B2

    公开(公告)日：2013-01-22

    申请号：US11766017

    申请日：2007-06-20

    Applicant: Subbu Ganesan ,  Ramesh Narayanaswamy ,  Ian Michael Nixon ,  Leonid Alexander Broukhis ,  Thomas Hanni Spencer

    Inventor： Subbu Ganesan ,  Ramesh Narayanaswamy ,  Ian Michael Nixon ,  Leonid Alexander Broukhis ,  Thomas Hanni Spencer

    IPC: G06F17/50

    CPC classification number: G06F17/5027

    Abstract: An RTL hardware description language simulation accelerator and circuit emulator which operates on data driven asynchronous completion handshaking principles. Deploying Muller C elements to control latches, the system does not depend on externally provided clocks or internal timing circuits with delay logic or clock generators. Each levelized domain of logic signals a successor level to begin execution of instructions with a level complete message produced when all its input operands have produced a completion message. Each predecessor stage holds back data production until the successor stage is ready. Each levelized data-driven asynchronous domain evaluation processor is self-timed receiving completion messages from its predecessors, and sending completion messages to its successors.

    Abstract translation: 一种用于数据驱动异步完成握手原理的RTL硬件描述语言模拟加速器和电路仿真器。 将Muller C元件部署到控制锁存器，系统不依赖于外部提供的时钟或具有延迟逻辑或时钟发生器的内部时序电路。 逻辑的每个等级化域发出后继级别，以在其所有输入操作数产生完成消息时产生的级别完成消息开始执行指令。 每个前身阶段都阻止数据生产，直到后续阶段准备就绪。 每个级别化的数据驱动的异步域评估处理器都是自动接收来自其前辈的完成消息，并将完成消息发送给其后继者。

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