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    METHOD FOR DELAY IMMUNE AND ACCELERATED EVALUATION OF DIGITAL CIRCUITS BY COMPILING ASYNCHRONOUS COMPLETION HANDSHAKING MEANS
    1.
    发明申请
    METHOD FOR DELAY IMMUNE AND ACCELERATED EVALUATION OF DIGITAL CIRCUITS BY COMPILING ASYNCHRONOUS COMPLETION HANDSHAKING MEANS 有权
    通过编写异步完成手段来延迟数字电路的延迟和数字电路的评估方法

    公开(公告)号：US20070294075A1

    公开(公告)日：2007-12-20

    申请号：US11766017

    申请日：2007-06-20

    Applicant: SUBBU GANESAN ,  RAMESH NARAYANASWAMY ,  IAN NIXON ,  LEONID BROUKHIS ,  THOMAS SPENCER

    Inventor： SUBBU GANESAN ,  RAMESH NARAYANASWAMY ,  IAN NIXON ,  LEONID BROUKHIS ,  THOMAS SPENCER

    IPC: G06F9/455

    CPC classification number: G06F17/5027

    Abstract: An RTL hardware description language simulation accelerator and circuit emulator which operates on data driven asynchronous completion handshaking principles. Deploying Muller C elements to control latches, the system does not depend on externally provided clocks or internal timing circuits with delay logic or clock generators. Each levelized domain of logic signals a successor level to begin execution of instructions with a level complete message produced when all its input operands have produced a completion message. Each predecessor stage holds back data production until the successor stage is ready. Each levelized data-driven asynchronous domain evaluation processor is self-timed receiving completion messages from its predecessors, and sending completion messages to its successors.

    Abstract translation: 一种用于数据驱动异步完成握手原理的RTL硬件描述语言模拟加速器和电路仿真器。 将Muller C元件部署到控制锁存器，系统不依赖于外部提供的时钟或具有延迟逻辑或时钟发生器的内部时序电路。 逻辑的每个等级化域发出后继级别，以在其所有输入操作数产生完成消息时产生的级别完成消息开始执行指令。 每个前身阶段都阻止数据生产，直到后续阶段准备就绪。 每个级别化的数据驱动的异步域评估处理器都是自动接收来自其前辈的完成消息，并将完成消息发送给其后继者。

    Tracing the change of state of a signal in a functional verification system
    3.
    发明授权
    Tracing the change of state of a signal in a functional verification system 失效

    公开(公告)号：US06629297B2

    公开(公告)日：2003-09-30

    申请号：US09738259

    申请日：2000-12-14

    Applicant: Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    Inventor： Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    IPC: G06F1750

    CPC classification number: G06F17/5022

    Abstract: Functional verification system enabling the state of difference signals to be traced. The signals represent the outputs resulting from the evaluation of combinatorial blocks and/or a plurality of state elements forming a target design. The combinatorial blocks and/or a plurality of state elements may be grouped into multiple clusters, with each cluster being identified by a cluster identifier. The tracing circuit may include a mask memory, a previous state memory, and trace controller. Each of the mask memory and the previous state memory may contain a number of locations equal to the number of clusters such that the relevant mask and previous state information may be accessed based on the cluster identifier. The trace controller receives evaluated outputs for a cluster at bit positions specified by a corresponding mask. The trace controller compares the received bits with the previous values, and generates an entry in a trace buffer to record any changes.

    Method for delay immune and accelerated evaluation of digital circuits by compiling asynchronous completion handshaking means
    4.
    发明授权
    Method for delay immune and accelerated evaluation of digital circuits by compiling asynchronous completion handshaking means 有权
    通过编译异步完成握手手段来延迟免疫和加速评估数字电路的方法

    公开(公告)号：US08359186B2

    公开(公告)日：2013-01-22

    申请号：US11766017

    申请日：2007-06-20

    Applicant: Subbu Ganesan ,  Ramesh Narayanaswamy ,  Ian Michael Nixon ,  Leonid Alexander Broukhis ,  Thomas Hanni Spencer

    Inventor： Subbu Ganesan ,  Ramesh Narayanaswamy ,  Ian Michael Nixon ,  Leonid Alexander Broukhis ,  Thomas Hanni Spencer

    IPC: G06F17/50

    CPC classification number: G06F17/5027

    Abstract: An RTL hardware description language simulation accelerator and circuit emulator which operates on data driven asynchronous completion handshaking principles. Deploying Muller C elements to control latches, the system does not depend on externally provided clocks or internal timing circuits with delay logic or clock generators. Each levelized domain of logic signals a successor level to begin execution of instructions with a level complete message produced when all its input operands have produced a completion message. Each predecessor stage holds back data production until the successor stage is ready. Each levelized data-driven asynchronous domain evaluation processor is self-timed receiving completion messages from its predecessors, and sending completion messages to its successors.

    Abstract translation: 一种用于数据驱动异步完成握手原理的RTL硬件描述语言模拟加速器和电路仿真器。 将Muller C元件部署到控制锁存器，系统不依赖于外部提供的时钟或具有延迟逻辑或时钟发生器的内部时序电路。 逻辑的每个等级化域发出后继级别，以在其所有输入操作数产生完成消息时产生的级别完成消息开始执行指令。 每个前身阶段都阻止数据生产，直到后续阶段准备就绪。 每个级别化的数据驱动的异步域评估处理器都是自动接收来自其前辈的完成消息，并将完成消息发送给其后继者。

    Functional verification system
    7.
    发明授权
    Functional verification system 失效
    功能验证系统

    公开(公告)号：US06691287B2

    公开(公告)日：2004-02-10

    申请号：US09738260

    申请日：2000-12-14

    Applicant: Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    Inventor： Subbu Ganesan ,  Leonid Alexander Broukhis ,  Ramesh Narayanaswamy ,  Ian Michael Nixon

    IPC: G06F1750

    CPC classification number: G06F17/5022

    Abstract: A functional verification system suited for verifying the function of non-cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

    Abstract translation: 一种适用于验证非循环集成电路（IC）设计功能的功能验证系统。 IC设计被分成连接顺序元件的多个组合块。 对应于分割块的真值表被计算并存储在存储器中。 通过评估块来确定IC设计的输出值。 评估通常需要一个存储器访问，因为真值表被预先计算并存储在存储器存储器中。 因此，输出值被快速计算。 存储是使用随机存取存储器实现的，并且XCON被设计为确保在评估期间依赖性被保留。

    Functional verification of integrated circuit designs
    10.
    发明授权
    Functional verification of integrated circuit designs 有权
    集成电路设计的功能验证

    公开(公告)号：US06629296B1

    公开(公告)日：2003-09-30

    申请号：US09627347

    申请日：2000-07-28

    Applicant: Subbu Ganesan ,  Shyam Prasad Pillalamarri

    Inventor： Subbu Ganesan ,  Shyam Prasad Pillalamarri

    IPC: G06F1750

    CPC classification number: G06F17/5022

    Abstract: A functional verification system suited for verifying the function of cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding to the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

    Abstract translation: 一种适用于验证基于循环的集成电路（IC）设计功能的功能验证系统。 IC设计被分成连接顺序元件的多个组合块。 计算与分割块对应的真值表，并将其存储在存储器中。 通过评估块来确定IC设计的输出值。 评估通常需要一个存储器访问，因为真值表被预先计算并存储在存储器存储器中。 因此，输出值被快速计算。 存储是使用随机存取存储器实现的，并且XCON被设计为确保在评估期间依赖性被保留。

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