公开(公告)号：US08543632B2

公开(公告)日：2013-09-24

申请号：US10458946

申请日：2003-06-11

申请人： Alexander Driker ,  Cristian Duroiu

发明人： Alexander Driker ,  Cristian Duroiu

IPC分类号： G06F7/38

CPC分类号： G06F7/49952 ,  G06F7/483

摘要： A method for computing the alignment sticky bit in floating-point operations is provided. The method includes computing a pre-computed sticky bit. A significand is aligned based on an alignment counter. A shifter sticky OR is computed. The alignment sticky bit is computed based on the pre-computed sticky bit by ORing the pre-computed sticky bit and the shifter sticky OR when the alignment counter comprises a value greater than or equal to a predefined value.

摘要翻译： 提供了一种用于计算浮点运算中的对齐粘性位的方法。 该方法包括计算预先计算的粘性位。 基于对齐计数器对齐一个有效数。 计算移位器粘性OR。 当对准计数器包括大于或等于预定值的值时，通过对预先计算的粘性位和移位器粘性OR进行OR运算，基于预计算的粘滞位来计算对准粘性位。

公开(公告)号：US07720898B2

公开(公告)日：2010-05-18

申请号：US10460019

申请日：2003-06-11

申请人： Alexander Driker ,  Cristian Duroiu

发明人： Alexander Driker ,  Cristian Duroiu

IPC分类号： G06F7/38

CPC分类号： G06F7/49936

摘要： A floating point unit, a central processing unit, and a method are provided for adjusting the exponent of a floating point number. During an addition or subtraction of two floating point numbers, the significand of the floating point result is rounded, and the exponent of the result may be adjusted due to normalization or renormalization. The exponent adjustment due to renormalization or the exponent adjustment due to normalization and renormalization is combined with the significand rounding operation.

摘要翻译： 提供浮点单元，中央处理单元和方法来调整浮点数的指数。 在两个浮点数的加法或减法期间，浮点结果的有效数被舍入，结果的指数可能由于归一化或重正化而被调整。 由归一化和重归一化引起的归一化或指数调整引起的指数调整与有效四舍五入操作相结合。

公开(公告)号：US06754807B1

公开(公告)日：2004-06-22

申请号：US09652450

申请日：2000-08-31

申请人： Sivagnanam Parthasarathy ,  Alexander Driker

发明人： Sivagnanam Parthasarathy ,  Alexander Driker

IPC分类号： G06F934

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： An apparatus for managing vertical dependencies between instructions in first and second instruction pipelines includes: 1) identifier (ID) reclaim circuitry for determining a sequential set of retired identifiers associated with retired instructions and for determining a next retire ID sequentially following the set; 2) first ID generation circuitry for sequentially assigning identifiers to destination registers associated with instructions entering the pipelines; 3) second ID generation circuitry associated with the first pipeline for identifying a first dependent source register associated with a first dependent source operand of a first instruction entering the first pipeline and assigning an ID of the first register to the first operand; and 4) instruction scheduling circuitry for comparing the first operand ID of the first instruction with the next retire ID and scheduling the first instruction for execution if the first operand ID is less than or equal to the next retire ID.

摘要翻译： 一种用于管理第一和第二指令流水线中的指令之间的垂直依赖性的装置，包括：1）标识符（ID）回收电路，用于确定与退休指令相关联的退休标识符的顺序集合，并用于依次确定该组之后的下一个退出ID; 2）用于将标识符顺序地分配给与进入管线的指令相关联的目的地寄存器的第一ID生成电路; 3）与第一流水线相关联的第二ID生成电路，用于识别与第一指令进入第一流水线的第一依赖源操作数相关联的第一依赖源寄存器，并将第一寄存器的ID分配给第一操作数; 以及4）指令调度电路，用于将第一指令的第一操作数ID与下一个退出ID进行比较，并且如果第一操作数ID小于或等于下一个退出ID，则调度第一指令执行。

公开(公告)号：US07600096B2

公开(公告)日：2009-10-06

申请号：US10299120

申请日：2002-11-19

申请人： Sivagnanam Parthasarathy ,  Alexander Driker

发明人： Sivagnanam Parthasarathy ,  Alexander Driker

IPC分类号： G06F15/80

CPC分类号： G06F9/3885 ,  G06F9/30043 ,  G06F9/30072

摘要： A processor architecture supports an electrical interface for coupling the processor core to one or more coprocessor extension units executing computational instructions, with a split-instruction transaction employed to provide operands and instructions to an extension unit and retrieve results from the extension unit. The generic instructions for sending an operation and data to the extension unit and/or retrieving data from the extension unit allow new computational instructions to be introduced without regeneration of the processor architecture. Support for multiple extension units and/or multiple execution pipes within each extension unit, multi-cycle execution latencies and different execution latencies between or within extension units, extension unit instruction predicates, and for handling processor core stalls and result save/restore on interrupt is included.

摘要翻译： 处理器架构支持用于将处理器核心耦合到执行计算指令的一个或多个协处理器扩展单元的电接口，其中分配指令事务用于向扩展单元提供操作数和指令，并从扩展单元检索结果。 用于向扩展单元发送操作和数据和/或从扩展单元检索数据的通用指令允许在不重新生成处理器架构的情况下引入新的计算指令。 支持每个扩展单元内的多个扩展单元和/或多个执行管道，多周期执行延迟和扩展单元之间或扩展单元指令谓词之间的不同执行延迟，以及用于处理中断的处理器内核停止和结果保存/恢复 包括。