公开(公告)号：US10929944B2

公开(公告)日：2021-02-23

申请号：US15360057

申请日：2016-11-23

申请人： Advanced Micro Devices, Inc.

发明人： Jiasheng Chen ,  Timour Paltashev ,  Alexander Lyashevsky ,  Carl Kittredge Wakeland ,  Michael J. Mantor

IPC分类号： G06T1/20 ,  G06F9/54 ,  G06F9/38 ,  G06T1/60

摘要： Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

公开(公告)号：US20180144435A1

公开(公告)日：2018-05-24

申请号：US15360057

申请日：2016-11-23

申请人： Advanced Micro Devices, Inc.

发明人： Jiasheng Chen ,  Timour Paltashev ,  Alexander Lyashevsky ,  Carl Kittredge Wakeland ,  Michael J. Mantor

IPC分类号： G06T1/20 ,  G06T1/60

CPC分类号： G06T1/20 ,  G06F9/3887 ,  G06F9/542 ,  G06F2009/3883 ,  G06F2209/548 ,  G06T1/60

摘要： Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

公开(公告)号：US11625807B2

公开(公告)日：2023-04-11

申请号：US17181300

申请日：2021-02-22

申请人： Advanced Micro Devices, Inc.

发明人： Jiasheng Chen ,  Timour Paltashev ,  Alexander Lyashevsky ,  Carl Kittredge Wakeland ,  Michael J. Mantor

IPC分类号： G06T1/20 ,  G06F9/54 ,  G06F9/38 ,  G06T1/60

摘要： Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

公开(公告)号：US20210201439A1

公开(公告)日：2021-07-01

申请号：US17181300

申请日：2021-02-22

申请人： Advanced Micro Devices, Inc.

发明人： Jiasheng Chen ,  Timour Paltashev ,  Alexander Lyashevsky ,  Carl Kittredge Wakeland ,  Michael J. Mantor

IPC分类号： G06T1/20 ,  G06F9/54 ,  G06F9/38 ,  G06T1/60

摘要： Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.