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公开(公告)号：US11789620B2
公开(公告)日：2023-10-17
申请号：US17560421
申请日：2021-12-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Scott P. Murphy , Huuhau M. Do
CPC classification number: G06F3/0629 , G06F3/0604 , G06F3/0673
Abstract: A phase training update circuit operates during a self-refresh cycle of a memory to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.
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公开(公告)号：US20240036748A1
公开(公告)日：2024-02-01
申请号：US18378893
申请日：2023-10-11
Applicant: Advanced Micro Devices, Inc.
Inventor： Scott P. Murphy , Huuhau M. Do
IPC: G06F3/06
CPC classification number: G06F3/0629 , G06F3/0673 , G06F3/0604
Abstract: A phase training update circuit operates to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.
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公开(公告)号：US12175102B2
公开(公告)日：2024-12-24
申请号：US18378893
申请日：2023-10-11
Applicant: Advanced Micro Devices, Inc.
Inventor： Scott P. Murphy , Huuhau M. Do
Abstract: A phase training update circuit operates to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.
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Patent Agency Ranking
公开(公告)号：US09965222B1
公开(公告)日：2018-05-08
申请号：US15299994
申请日：2016-10-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin M. Brandl , Scott P. Murphy , James R. Magro , Paramjit K. Lubana
CPC classification number: G06F11/073 , G06F11/0793 , G06F13/16
Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor includes a memory controller coupled to the memory channel and is adapted to access at least one rank of double data rate memory. The memory controller includes a command queue for storing received memory access requests, and an arbiter for picking memory access requests from the command queue, and then providing the memory access requests to the memory channel. The memory access requests are selected based on predetermined criteria, and in response to a mode register access request to quiesce pending operations. Additionally, the memory controller includes a mode register access controller that in response to the mode register access request, generates at least one corresponding mode register set command to a memory bus. The memory controller then relinquishes control of the memory bus to the arbiter thereafter.
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公开(公告)号：US20180018221A1
公开(公告)日：2018-01-18
申请号：US15375076
申请日：2016-12-09
Applicant: Advanced Micro Devices, Inc.
Inventor： James R. Magro , Ruihua Peng , Anthony Asaro , Kedarnath Balakrishnan , Scott P. Murphy , YuBin Yao
CPC classification number: G06F11/1016 , G06F11/10 , G06F13/1626 , G06F13/4022
Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.
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公开(公告)号：US20230205435A1
公开(公告)日：2023-06-29
申请号：US17560421
申请日：2021-12-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Scott P. Murphy , Huuhau M. Do
IPC: G06F3/06
CPC classification number: G06F3/0629 , G06F3/0604 , G06F3/0673
Abstract: A phase training update circuit operates during a self-refresh cycle of a memory to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.
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公开(公告)号：US11675659B2
公开(公告)日：2023-06-13
申请号：US15375076
申请日：2016-12-09
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： James R. Magro , Ruihua Peng , Anthony Asaro , Kedarnath Balakrishnan , Scott P. Murphy , YuBin Yao
CPC classification number: G06F11/1016 , G06F11/10 , G06F13/1626 , G06F13/4022
Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.
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公开(公告)号：US20180113648A1
公开(公告)日：2018-04-26
申请号：US15299994
申请日：2016-10-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin M. Brandl , Scott P. Murphy , James R. Magro , Paramjit K. Lubana
CPC classification number: G06F11/073 , G06F11/0793 , G06F13/16
Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor includes a memory controller coupled to the memory channel and is adapted to access at least one rank of double data rate memory. The memory controller includes a command queue for storing received memory access requests, and an arbiter for picking memory access requests from the command queue, and then providing the memory access requests to the memory channel. The memory access requests are selected based on predetermined criteria, and in response to a mode register access request to quiesce pending operations. Additionally, the memory controller includes a mode register access controller that in response to the mode register access request, generates at least one corresponding mode register set command to a memory bus. The memory controller then relinquishes control of the memory bus to the arbiter thereafter.
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