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公开(公告)号：US12175102B2
公开(公告)日：2024-12-24
申请号：US18378893
申请日：2023-10-11
Applicant: Advanced Micro Devices, Inc.
Inventor： Scott P. Murphy , Huuhau M. Do
Abstract: A phase training update circuit operates to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.
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公开(公告)号：US11789620B2
公开(公告)日：2023-10-17
申请号：US17560421
申请日：2021-12-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Scott P. Murphy , Huuhau M. Do
CPC classification number: G06F3/0629 , G06F3/0604 , G06F3/0673
Abstract: A phase training update circuit operates during a self-refresh cycle of a memory to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.
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公开(公告)号：US20240036748A1
公开(公告)日：2024-02-01
申请号：US18378893
申请日：2023-10-11
Applicant: Advanced Micro Devices, Inc.
Inventor： Scott P. Murphy , Huuhau M. Do
IPC: G06F3/06
CPC classification number: G06F3/0629 , G06F3/0673 , G06F3/0604
Abstract: A phase training update circuit operates to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.
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公开(公告)号：US20230205435A1
公开(公告)日：2023-06-29
申请号：US17560421
申请日：2021-12-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Scott P. Murphy , Huuhau M. Do
IPC: G06F3/06
CPC classification number: G06F3/0629 , G06F3/0604 , G06F3/0673
Abstract: A phase training update circuit operates during a self-refresh cycle of a memory to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.
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