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    Using Neural Networks to Handle Watermarks in Digital Files
    1.
    发明申请
    Using Neural Networks to Handle Watermarks in Digital Files 有权

    公开(公告)号：US20220414456A1

    公开(公告)日：2022-12-29

    申请号：US17362661

    申请日：2021-06-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Nicholas P. Malaya ,  William W. Freitag, JR.

    IPC: G06N3/08 ,  G06N3/04

    Abstract: The described embodiments include an electronic device having a processor. The processor performs operations for handling watermarks in files. As part of the operations, the processor processes a portion of a file in a classification neural network to determine whether a watermark is present in the portion of the file. Based on a result of the processing, the processor performs an update associated with the watermark in the portion of the file. The processor then provides the updated portion of the file.

    Dynamic, variable bit-width numerical precision on field-programmable gate arrays for machine learning tasks
    2.
    发明授权
    Dynamic, variable bit-width numerical precision on field-programmable gate arrays for machine learning tasks 有权

    公开(公告)号：US11216250B2

    公开(公告)日：2022-01-04

    申请号：US15833287

    申请日：2017-12-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Nicholas P. Malaya ,  Elliot H. Mednick

    IPC: G06F7/57 ,  G06N3/04 ,  H03K19/17728 ,  G06N3/08 ,  G06N3/063 ,  G06F7/544

    Abstract: A method includes providing a set of one or more computational units implemented in a set of one or more field programmable gate array (FPGA) devices, where the set of one or more computational units is configured to generate a plurality of output values based on one or more input values. The method further includes, for each computational unit of the set of computational units, performing a first calculation in the computational unit using a first number representation, where a first output of the plurality of output values is based on the first calculation, determining a second number representation based on the first output value, and performing a second calculation in the computational unit using the second number representation, where a second output of the plurality of output values is based on the second calculation.

    Configuring computational elements for performing a training operation for a generative adversarial network
    3.
    发明授权
    Configuring computational elements for performing a training operation for a generative adversarial network 有权

    公开(公告)号：US11481637B2

    公开(公告)日：2022-10-25

    申请号：US16009089

    申请日：2018-06-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Nicholas P. Malaya

    IPC: G06N3/08

    Abstract: An electronic device that includes a controller functional block and a computational functional block having one or more computational elements performs operations associated with a training operation for a generative adversarial network, the generative adversarial network including a generative network and a discriminative network. The controller functional block determines one or more characteristics of the generative adversarial network. Based on the one or more characteristics, the controller functional block configures the one or more computational elements to perform processing operations for each of the generative network and the discriminative network during the training operation for the generative adversarial network.

    Configuring Computational Elements for Performing a Training Operation for a Generative Adversarial Network
    6.
    发明申请
    Configuring Computational Elements for Performing a Training Operation for a Generative Adversarial Network 审中-公开

    公开(公告)号：US20190385064A1

    公开(公告)日：2019-12-19

    申请号：US16009089

    申请日：2018-06-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Nicholas P. Malaya

    IPC: G06N3/08

    Abstract: An electronic device that includes a controller functional block and a computational functional block having one or more computational elements performs operations associated with a training operation for a generative adversarial network, the generative adversarial network including a generative network and a discriminative network. The controller functional block determines one or more characteristics of the generative adversarial network. Based on the one or more characteristics, the controller functional block configures the one or more computational elements to perform processing operations for each of the generative network and the discriminative network during the training operation for the generative adversarial network.

    DYNAMIC, VARIABLE BIT-WIDTH NUMERICAL PRECISION ON FPGAS FOR MACHINE LEARNING TASKS
    7.
    发明申请
    DYNAMIC, VARIABLE BIT-WIDTH NUMERICAL PRECISION ON FPGAS FOR MACHINE LEARNING TASKS 审中-公开

    公开(公告)号：US20190171420A1

    公开(公告)日：2019-06-06

    申请号：US15833287

    申请日：2017-12-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Nicholas P. Malaya ,  Elliot H. Mednick

    IPC: G06F7/57 ,  G06N3/04 ,  G06F7/544 ,  H03K19/177

    Abstract: A method includes providing a set of one or more computational units implemented in a set of one or more field programmable gate array (FPGA) devices, where the set of one or more computational units is configured to generate a plurality of output values based on one or more input values. The method further includes, for each computational unit of the set of computational units, performing a first calculation in the computational unit using a first number representation, where a first output of the plurality of output values is based on the first calculation, determining a second number representation based on the first output value, and performing a second calculation in the computational unit using the second number representation, where a second output of the plurality of output values is based on the second calculation.

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