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公开(公告)号：US10671722B2
公开(公告)日：2020-06-02
申请号：US15230388
申请日：2016-08-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Gabriel H Loh , Maurice B Steinman
Abstract: A host system-on-chip (SoC) includes a network on chip (NoC) for transmitting local traffic between internal blocks of the SoC, an external processor link for receiving messages at the host SoC from an untrusted device. A traffic controller in the host SoC that is coupled with the external processor link monitors an amount of external traffic from the untrusted device over a set of one or more time intervals, detects a violation of a traffic policy based on the amount of external traffic, and in response to detecting the violation, reduces traffic in the NoC resulting from the messages from the untrusted device.
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公开(公告)号：US11275829B2
公开(公告)日：2022-03-15
申请号：US16857058
申请日：2020-04-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Gabriel H Loh , Maurice B Steinman
Abstract: An apparatus includes an external device for causing messages to be transmitted with local traffic between internal blocks of a host system-on-chip (SoC) via a network on chip (NoC) in the host SoC, the transmitted messages including one or more memory requests directed to a memory of the host SoC, violating a traffic policy for a first time interval by transmitting a number of messages that exceeds a maximum threshold of for the first time interval, where the SoC monitors an amount of external traffic from an untrusted device transmitted over the NoC over a set of one or more time intervals including the first time interval, and in response to detection of the violation by the host SoC, reducing an amount of traffic transmitted via the NoC. The apparatus also includes an external processor link for transmitting the messages from the external device to the host SoC.
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公开(公告)号：US08959372B2
公开(公告)日：2015-02-17
申请号：US13919306
申请日：2013-06-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Branover , Maurice B Steinman , William L Bircher
CPC classification number: G06F1/3215 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.
Abstract translation: 公开了一种用于处理节点的性能控制的装置和方法。 在一个实施例中，系统包括处理节点和功率管理单元，其被配置为针对多个时间间隔中的每一个监视处理节点的活动级别，使处理节点在连续的连续操作期间在高操作点 时间间隔，如果给定间隔中的活动水平大于高活动阈值，则如果活动水平低于低活动阈值，则在低操作点操作至少一个连续时间间隔，或使得操作系统软件能够使 处理节点在多个操作点的一个或多个预定义的中间操作点之一操作，如果活动水平小于高活动阈值并且大于低活动阈值。
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