公开(公告)号：US12158842B2

公开(公告)日：2024-12-03

申请号：US17956995

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Benjamin Youngjae Cho ,  Armand Bahram Behroozi ,  Michael L. Chu ,  Ashwin Aji

IPC: G06F12/02 ,  G06F12/06

Abstract: A processing system allocates memory to co-locate input and output operands for operations for processing in memory (PIM) execution in the same PIM-local memory while exploiting row-buffer locality and complying with conventional memory abstraction. The processing system identifies as “super rows” virtual rows that span all the banks of a memory device. Each super row has a different bank-interleaving pattern, referred to as a “color”. A group of contiguous super rows that has the same PIM-interleaving pattern is referred to as a “color group”. The processing system assigns memory addresses to each operand (e.g., vector) of an operation for PIM execution to a super row having a different color within the same color group to co-locate the operands for each PIM execution unit and uses address hashing to alternate between banks assigned to elements of a first operand and elements of a second operand of the operation.

公开(公告)号：US20240272791A1

公开(公告)日：2024-08-15

申请号：US18108653

申请日：2023-02-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Youngjae Cho ,  Armand Bahram Behroozi ,  Michael L. Chu ,  Emily Anne Furst

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0671 ,  G06F9/4881 ,  G06F9/5016 ,  G06F9/5066

Abstract: Automatic generation of data layout instructions for locating data objects in memory that are involved in a sequence of operations for a computational task is described. In accordance with the described techniques, an interference graph is generated for the sequence of operations, where individual nodes in the interference graph represent data objects involved in the computational task. The interference graph includes edges connecting different pairs of nodes, such that an edge indicates the connected data objects are involved in a common operation of the sequence of operations. Weights are assigned to edges based on architectural characteristics of a system performing the computational task as well as a size of the data objects connected by an edge. Individual data objects are then assigned to locations in memory based on edge weights of edges connected to a node representing the data object, optimizing system performance during the computational task.

公开(公告)号：US20240111672A1

公开(公告)日：2024-04-04

申请号：US17956995

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Benjamin Youngjae Cho ,  Armand Bahram Behroozi ,  Michael L. Chu ,  Ashwin Aji

IPC: G06F12/06 ,  G06F12/02

CPC classification number: G06F12/0607 ,  G06F12/0223 ,  G06F2212/1024

Abstract: A processing system allocates memory to co-locate input and output operands for operations for processing in memory (PIM) execution in the same PIM-local memory while exploiting row-buffer locality and complying with conventional memory abstraction. The processing system identifies as “super rows” virtual rows that span all the banks of a memory device. Each super row has a different bank-interleaving pattern, referred to as a “color”. A group of contiguous super rows that has the same PIM-interleaving pattern is referred to as a “color group”. The processing system assigns memory addresses to each operand (e.g., vector) of an operation for PIM execution to a super row having a different color within the same color group to co-locate the operands for each PIM execution unit and uses address hashing to alternate between banks assigned to elements of a first operand and elements of a second operand of the operation.