公开(公告)号：US20160062388A1

公开(公告)日：2016-03-03

申请号：US14935679

申请日：2015-11-09

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  James E. Burnette, II

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G01R31/31709 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/31858 ,  G01R31/318594 ,  G11B20/10398 ,  H03M1/0836 ,  H03M1/205 ,  H04L1/205

Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

Abstract translation: 公开了可以允许在时钟分配网络中检测周期和相位抖动的抖动检测电路的实施例。 抖动检测电路可以包括相位选择器，数据发生器，延迟链，逻辑电路和时钟存储元件。 相位选择器可以用于选择要用于发射时钟的时钟相位，并且数据发生器可以用于响应于发射时钟产生数据信号。 延迟链可以产生取决于数据信号的多个输出，并且时钟控制的存储元件可以用于从延迟链捕获多个输出，其可以通过逻辑电路与预期数据进行比较。

公开(公告)号：US20140129884A1

公开(公告)日：2014-05-08

申请号：US13670739

申请日：2012-11-07

Applicant: APPLE INC.

Inventor： Greg M. Hess ,  James E. Burnette, II

IPC: G06F11/263

CPC classification number: G11C29/50012 ,  G11C8/16

Abstract: Embodiments of a register file test circuit are disclosed that may allow for determining write performance at low power supply voltages. The register file test circuit may include a decoder, a multiplexer, a frequency divider, and a control circuit. The decoder may be operable to select a register cell within a register file, and the control circuit may be operable to controllably activate the read and write paths through the selected register cell, allowing data read to be inverted and re-written back into the selected register cell.

Abstract translation: 公开了寄存器文件测试电路的实施例，其可以允许在低电源电压下确定写入性能。 寄存器文件测试电路可以包括解码器，复用器，分频器和控制电路。 解码器可以用于选择寄存器文件中的寄存器单元，并且控制电路可操作以可控制地激活通过所选择的寄存器单元的读取和写入路径，从而允许将数据读取反向并重写回所选择的寄存器单元 寄存器单元格。

公开(公告)号：US09389635B2

公开(公告)日：2016-07-12

申请号：US14935679

申请日：2015-11-09

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  James E. Burnette, II

IPC: G01R31/28 ,  G06F1/04 ,  G01R31/3185 ,  G01R31/317 ,  H03M1/08 ,  H03M1/20 ,  H04L1/20 ,  G11B20/10

CPC classification number: G06F1/04 ,  G01R31/31709 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/31858 ,  G01R31/318594 ,  G11B20/10398 ,  H03M1/0836 ,  H03M1/205 ,  H04L1/205

Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

公开(公告)号：US20140126312A1

公开(公告)日：2014-05-08

申请号：US13670813

申请日：2012-11-07

Applicant: APPLE INC.

Inventor： Greg M. Hess ,  James E. Burnette, II

IPC: H03F3/45 ,  G01R31/316 ,  G11C29/00

CPC classification number: H01L22/12 ,  G11C29/026 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of a sense amplifier test circuit are disclosed that may allow for detecting soft failures. The sense amplifier test circuit may include a voltage generator circuit, a sense amplifier, and a detection circuit. The voltage generator may be operable to controllably supply different differential voltages to the sense amplifier, and the detection circuit may be operable to detect an analog voltage on the output of the sense amplifier.

Abstract translation: 公开了可以允许检测软故障的读出放大器测试电路的实施例。 读出放大器测试电路可以包括电压发生器电路，读出放大器和检测电路。 电压发生器可操作以可控制地向感测放大器提供不同的差分电压，并且检测电路可以用于检测读出放大器的输出上的模拟电压。