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    MULTI-THREAD PROCESSING
    2.
    发明申请
    MULTI-THREAD PROCESSING 有权

    公开(公告)号：US20210049014A1

    公开(公告)日：2021-02-18

    申请号：US16806937

    申请日：2020-03-02

    Applicant: Advanced New Technologies Co.. Ltd.

    Inventor： Ling Ma ,  Wei Zhou ,  Changhua He

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A computer-implemented method for multi-thread processing, the method including: compiling a first plurality of threads using a corresponding first register set for each thread in the first plurality of threads, to obtain a first plurality of corresponding machine instruction codes; and fusing the first plurality of machine instruction codes using first instructions in an instruction set supported by a processing core, to obtain machine instruction code of a fused thread, the machine instruction code of the fused thread including thread portions corresponding to each thread of the first plurality of threads, in which the first instructions include load effective address instructions and control transfer instructions, in which the load effective address instructions and the control transfer instructions are compiled using a second register set, and in which jump operations between thread portions are implemented by the control transfer instructions inserted into the machine instruction code of the fused thread.

    Multi-thread processing
    3.
    发明授权
    Multi-thread processing 有权

    公开(公告)号：US11216278B2

    公开(公告)日：2022-01-04

    申请号：US16806937

    申请日：2020-03-02

    Applicant: Advanced New Technologies Co., Ltd.

    Inventor： Ling Ma ,  Wei Zhou ,  Changhua He

    IPC: G06F9/44 ,  G06F9/30 ,  G06F9/38 ,  G06F8/41

    Abstract: A computer-implemented method for multi-thread processing, the method including: compiling a first plurality of threads using a corresponding first register set for each thread in the first plurality of threads, to obtain a first plurality of corresponding machine instruction codes; and fusing the first plurality of machine instruction codes using first instructions in an instruction set supported by a processing core, to obtain machine instruction code of a fused thread, the machine instruction code of the fused thread including thread portions corresponding to each thread of the first plurality of threads, in which the first instructions include load effective address instructions and control transfer instructions, in which the load effective address instructions and the control transfer instructions are compiled using a second register set, and in which jump operations between thread portions are implemented by the control transfer instructions inserted into the machine instruction code of the fused thread.

    Method, apparatus, and electronic device for improving CPU performance
    4.
    发明授权
    Method, apparatus, and electronic device for improving CPU performance 有权

    公开(公告)号：US10983839B2

    公开(公告)日：2021-04-20

    申请号：US16743971

    申请日：2020-01-15

    Applicant: Advanced New Technologies Co., Ltd.

    Inventor： Ling Ma ,  Changhua He

    IPC: G06F9/52 ,  G06F9/50 ,  G06F9/38 ,  G06F16/176 ,  G06F13/36

    Abstract: Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.

    Method and apparatus for updating shared data in a multi-core processor environment
    5.
    发明授权
    Method and apparatus for updating shared data in a multi-core processor environment 有权

    公开(公告)号：US11106795B2

    公开(公告)日：2021-08-31

    申请号：US16660563

    申请日：2019-10-22

    Applicant: ADVANCED NEW TECHNOLOGIES CO., LTD.

    Inventor： Ling Ma ,  Changhua He

    IPC: G06F9/54 ,  G06F21/57 ,  G06F9/48 ,  G06F15/80

    Abstract: Embodiments of the specification provide a method and an apparatus for updating shared data in a multi-core processor environment. The multi-processor environment comprises a multi-core processor. The multi-core processor comprises a plurality of separate processing units (referred to as cores, or core processing units (CPUs) in the specification); the multi-core processor is configured to process a multi-threaded task; the multi-threaded task has shared data to update. The method is executed by any CPU. The method may comprise: requesting, by a first CPU, for a lock to execute a critical section function on the shared data, wherein the lock provides permission to update the shared data, and the critical section function updates the shared data; and setting, by the first CPU if the lock is occupied by a second CPU, a memory index corresponding to the critical section function in a memory of the lock for the second CPU to execute the critical section function based on the memory index.

    Method, apparatus, and electronic device for improving parallel performance of CPU
    6.
    发明授权
    Method, apparatus, and electronic device for improving parallel performance of CPU 有权

    公开(公告)号：US11080094B2

    公开(公告)日：2021-08-03

    申请号：US16945589

    申请日：2020-07-31

    Applicant: Advanced New Technologies Co., Ltd.

    Inventor： Ling Ma ,  Wei Zhou ,  Changhua He

    IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

    Abstract: Implementations of the present specification provide a method, an apparatus, and an electronic device for improving parallel performance of a CPU. The method includes: attempting to acquire data requests that are of a same type and that are allocated to the CPU core; determining a number of requests that are specified by the acquired one or more data requests; and in response to determining that the number of requests is greater than or equal to a maximum degree of parallelism: executing executable codes corresponding to the maximum degree of parallelism, wherein the maximum degree of parallelism is a maximum number of parallel threads executable by the CPU, and wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism at a time that is prior to a time of the executing.

    Method, apparatus, and electronic device for improving CPU performance
    7.
    发明授权
    Method, apparatus, and electronic device for improving CPU performance 有权

    公开(公告)号：US11269693B2

    公开(公告)日：2022-03-08

    申请号：US17234313

    申请日：2021-04-19

    Applicant: Advanced New Technologies Co., Ltd.

    Inventor： Ling Ma ,  Changhua He

    IPC: G06F9/52 ,  G06F9/50 ,  G06F9/38 ,  G06F16/176 ,  G06F13/36

    Abstract: Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.

    METHOD, APPARATUS, AND ELECTRONIC DEVICE FOR IMPROVING CPU PERFORMANCE
    8.
    发明申请
    METHOD, APPARATUS, AND ELECTRONIC DEVICE FOR IMPROVING CPU PERFORMANCE 有权

    公开(公告)号：US20210240547A1

    公开(公告)日：2021-08-05

    申请号：US17234313

    申请日：2021-04-19

    Applicant: Advanced New Technologies Co., Ltd.

    Inventor： Ling Ma ,  Changhua He

    IPC: G06F9/52 ,  G06F9/38 ,  G06F9/50

    Abstract: Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.

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