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公开(公告)号：US20130060545A1
公开(公告)日：2013-03-07
申请号：US13226513
申请日：2011-09-07
申请人： Hana Chockler , Alexander Ivrii , Arie Matsliah , Shiri Moran , Ziv Nevo
发明人： Hana Chockler , Alexander Ivrii , Arie Matsliah , Shiri Moran , Ziv Nevo
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Method, apparatus, and product for performing incremental formal verification. A computer-implemented method performed by a computerized device. The method comprises: obtaining invariants with respect to a first model; determining a portion of the invariants that are invariants with respect to a second model, and utilizing the portion of the invariants to check that the second model holds a property.
摘要翻译： 执行递增形式验证的方法，设备和产品。 由计算机化设备执行的计算机实现的方法。 该方法包括：获得关于第一模型的不变量; 确定相对于第二模型是不变量的不变量的一部分，以及利用所述不变量的所述部分来检查所述第二模型是否具有属性。
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公开(公告)号：US08127261B2
公开(公告)日：2012-02-28
申请号：US12356116
申请日：2009-01-20
申请人： Gadiel Auerbach , Matan Gal , Ziv Nevo
发明人： Gadiel Auerbach , Matan Gal , Ziv Nevo
CPC分类号： G06F8/34
摘要： Computer-implemented techniques are disclosed for defining an environment for formal verification of a design-under-test. Initially there is extraction of design inputs by a design analysis module, and presentation of the inputs on a graphical user interface. Behavior options for the design inputs are offered on the graphical user interface for selection by an operator. Environment code that is descriptive of the design inputs and selected behavior options is emitted, typically in a hardware description language, for submission to a formal verification tool. A meta-code file containing the assigned behavior options is generated to aid subsequent sessions.
摘要翻译： 公开了计算机实现的技术来定义用于正在验证被测设计的环境。 最初由设计分析模块提取设计输入，并在图形用户界面上显示输入。 设计输入的行为选项在图形用户界面上提供，供操作员选择。 描述设计输入和所选行为选项的环境代码通常以硬件描述语言发出，以提交给正式的验证工具。 生成包含分配的行为选项的元代码文件以辅助后续会话。
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公开(公告)号：US20110071809A1
公开(公告)日：2011-03-24
申请号：US12564931
申请日：2009-09-23
申请人： Sharon Keidar-Barner , Shiri Moran , Ziv Nevo , Sitvanit Ruah , Tatyana Veksler
发明人： Sharon Keidar-Barner , Shiri Moran , Ziv Nevo , Sitvanit Ruah , Tatyana Veksler
IPC分类号： G06G7/48
CPC分类号： G06F17/504
摘要： A model may comprise finite paths in respect to a constraint. The model and the constraint may be modified such that a portion of the limitations induces by the constraint is injected to the model. Adding the limitation directly to the model may be expressed by a reduction of a measurement of nondeterminism in the model. The model may be modified based on the constraint, and the constraint may be modified based on the model. The constraint may be strengthened to provide for an early finite path detection.
摘要翻译： 模型可以包括关于约束的有限路径。 可以修改模型和约束，使得由约束引起的限制的一部分被注入到模型中。 可以通过减少模型中非确定性的测量来表示将限制直接添加到模型中。 可以基于约束修改模型，并且可以基于模型修改约束。 可以加强约束以提供早期的有限路径检测。
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公开(公告)号：US07131085B2
公开(公告)日：2006-10-31
申请号：US10813239
申请日：2004-03-30
申请人： Monica Farkash , Ziv Nevo
发明人： Monica Farkash , Ziv Nevo
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for verification of a system design represented by a model that includes a plurality of variables. The method includes arranging the variables in an Ordered Binary Decision Diagram (OBDD) according to an initial order of the variables, the OBDD including a number of nodes arranged in rows corresponding respectively to the plurality of the variables. Each processor, among a group of two or more computer processors, is assigned a respective variable among the plurality of the variables. Using each processor, the rows of the OBDD are reordered by varying a position in the OBDD of the row corresponding to the respective variable that is assigned to the processor until at least one of the processors identifies a new order for the OBDD. The new order of the OBDD may be used to verify a characteristic of the model against a specification.
摘要翻译： 一种用于验证由包括多个变量的模型表示的系统设计的方法。 该方法包括根据变量的初始顺序将变量排列在有序二进制决策图（OBDD）中，OBDD包括分别排列在与多个变量对应的行中的多个节点。 在一组两个或更多个计算机处理器中的每个处理器在多个变量中分配相应的变量。 使用每个处理器，通过改变对应于分配给处理器的相应变量的行的OBDD中的位置来重新排序OBDD的行，直到至少一个处理器识别OBDD的新订单。 OBDD的新顺序可用于根据规范验证模型的特性。
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公开(公告)号：US08996339B2
公开(公告)日：2015-03-31
申请号：US13226513
申请日：2011-09-07
申请人： Hana Chockler , Alexander Ivrii , Arie Matsliah , Shiri Moran , Ziv Nevo
发明人： Hana Chockler , Alexander Ivrii , Arie Matsliah , Shiri Moran , Ziv Nevo
CPC分类号： G06F17/504
摘要： Method, apparatus, and product for performing incremental formal verification. A computer-implemented method performed by a computerized device. The method comprises: obtaining invariants with respect to a first model; determining a portion of the invariants that are invariants with respect to a second model, and utilizing the portion of the invariants to check that the second model holds a property.
摘要翻译： 执行递增形式验证的方法，设备和产品。 由计算机化设备执行的计算机实现的方法。 该方法包括：获得关于第一模型的不变量; 确定相对于第二模型是不变量的不变量的一部分，以及利用所述不变量的所述部分来检查所述第二模型是否具有属性。
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公开(公告)号：US08352234B2
公开(公告)日：2013-01-08
申请号：US12564931
申请日：2009-09-23
申请人： Sharon Keidar Barner , Shiri Moran , Ziv Nevo , Sitvanit Ruah , Tatyana Veksler
发明人： Sharon Keidar Barner , Shiri Moran , Ziv Nevo , Sitvanit Ruah , Tatyana Veksler
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A computerized system comprising: a processor; a first interface configured to obtain a constraint; a second interface configured to obtain a first model, wherein the first model is configured to be utilized in model checking, and the first model, when constrained by the constraint, comprises at least one finite path; and a finite path removal module implemented in the processor and configured to generate a second model equivalent to the first model obtained by said second interface, wherein the second model excludes a portion of the at least one finite path, and the second model is configured to be utilized in model checking.
摘要翻译： 一种计算机化系统，包括：处理器; 配置为获得约束的第一接口; 第二接口，被配置为获得第一模型，其中所述第一模型被配置为在模型检查中使用，并且当受约束约束时，所述第一模型包括至少一个有限路径; 以及有限路径去除模块，其在所述处理器中实现并且被配置为生成等效于由所述第二接口获得的所述第一模型的第二模型，其中所述第二模型排除所述至少一个有限路径的一部分，并且所述第二模型被配置为 用于模型检查。
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公开(公告)号：US20110022373A1
公开(公告)日：2011-01-27
申请号：US12507099
申请日：2009-07-22
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Phase abstraction may be utilized to increase efficiency of model checking techniques. A liveness property may be checked in respect to a phase abstracted model by modifying the liveness property in accordance with the phase abstracted model. A fairness property may be modified to ensure that the fairness property is held by the model checker. A counter-example produced by a model checker is modified to be in accordance to an original model. The counter-example comprises a repetitive behavior. The counter-example may be modified to shorten the repetitive behavior or to apply the repetitive behavior in an earlier cycle of the counter-example.
摘要翻译： 可以利用相位抽象来提高模型检查技术的效率。 可以通过根据相位抽象模型修改活性属性来检查相位抽象模型的活跃性。 可以修改公平财产，以确保公平性由模型检查员持有。 由模型检查器产生的对照例被修改为与原始模型一致。 反例包括重复行为。 可以修改对照例以缩短重复行为或者在反例的早期循环中应用重复行为。
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8.发明申请Formal Verification of Models Using Concurrent Model-Reduction and Model-Checking 失效使用并发模型减少和模型检查的模型的正式验证公开(公告)号：US20090326886A1
公开(公告)日：2009-12-31
申请号：US12164144
申请日：2008-06-30
申请人： Eli Arbel , Shaked Flur , Ziv Nevo , Michael Shamis
发明人： Eli Arbel , Shaked Flur , Ziv Nevo , Michael Shamis
CPC分类号： G06F11/3608
摘要： Formal verification of models using concurrent model-reduction and model-checking. For example, a system for formal verification of models includes: one or more model reducers to reduce a model; one or more model checkers to check the model, wherein at least one of the model reducers is to run concurrently with at least one of the model checkers; and a model synchronizer to synchronize information between at least one of the model reducers and at least one of the model checkers.
摘要翻译： 使用并发模型减少和模型检查的模型的正式验证。 例如，用于形式验证模型的系统包括：一个或多个减少模型的模型减少器; 一个或多个模型检查器来检查模型，其中模型缩减器中的至少一个与至少一个模型检查器同时运行; 以及模型同步器，用于在至少一个模型减少器与至少一个模型检查器之间同步信息。
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公开(公告)号：US08627273B2
公开(公告)日：2014-01-07
申请号：US12507099
申请日：2009-07-22
IPC分类号： G06F9/44
CPC分类号： G06F17/504
摘要： Phase abstraction may be utilized to increase efficiency of model checking techniques. A liveness property may be checked in respect to a phase abstracted model by modifying the liveness property in accordance with the phase abstracted model. A fairness property may be modified to ensure that the fairness property is held by the model checker. A counter-example produced by a model checker is modified to be in accordance to an original model. The counter-example comprises a repetitive behavior. The counter-example may be modified to shorten the repetitive behavior or to apply the repetitive behavior in an earlier cycle of the counter-example.
摘要翻译： 可以利用相位抽象来提高模型检查技术的效率。 可以通过根据相位抽象模型修改活性属性来检查相位抽象模型的活跃性。 可以修改公平财产，以确保公平性由模型检查员持有。 由模型检查器产生的对照例被修改为与原始模型一致。 反例包括重复行为。 可以修改对照例以缩短重复行为或者在反例的早期循环中应用重复行为。
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10.发明授权Formal verification of models using concurrent model-reduction and model-checking 失效使用并发模型减少和模型检查的模型的正式验证公开(公告)号：US08244516B2
公开(公告)日：2012-08-14
申请号：US12164144
申请日：2008-06-30
申请人： Eli Arbel , Shaked Flur , Ziv Nevo , Michael Shamis
发明人： Eli Arbel , Shaked Flur , Ziv Nevo , Michael Shamis
CPC分类号： G06F11/3608
摘要： Formal verification of models using concurrent model-reduction and model-checking. For example, a system for formal verification of models includes: one or more model reducers to reduce a model; one or more model checkers to check the model, wherein at least one of the model reducers is to run concurrently with at least one of the model checkers; and a model synchronizer to synchronize information between at least one of the model reducers and at least one of the model checkers.
摘要翻译： 使用并发模型减少和模型检查的模型的正式验证。 例如，用于形式验证模型的系统包括：一个或多个减少模型的模型减少器; 一个或多个模型检查器来检查模型，其中模型缩减器中的至少一个与至少一个模型检查器同时运行; 以及模型同步器，用于在至少一个模型减少器与至少一个模型检查器之间同步信息。
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