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    Characterizing circuit performance by separating device and interconnect impact on signal delay
    1.
    发明申请
    Characterizing circuit performance by separating device and interconnect impact on signal delay 有权
    通过分离器件和互连对信号延迟的影响来表征电路性能

    公开(公告)号：US20050149777A1

    公开(公告)日：2005-07-07

    申请号：US10742300

    申请日：2003-12-18

    申请人： Xiao-Jie Yuan ,  Michael Hart ,  Zicheng Ling ,  Steven Young

    发明人： Xiao-Jie Yuan ,  Michael Hart ,  Zicheng Ling ,  Steven Young

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G01R31/3187 ,  G11B5/00 ,  G01R31/02 ,  G06K5/04 ,  G11B20/20

    CPC分类号： G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

    摘要翻译： 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

    Characterizing circuit performance by separating device and interconnect impact on signal delay
    2.
    发明申请
    Characterizing circuit performance by separating device and interconnect impact on signal delay 有权

    公开(公告)号：US20060267618A1

    公开(公告)日：2006-11-30

    申请号：US11498371

    申请日：2006-08-03

    申请人： Xiao-Jie Yuan ,  Michael Hart ,  Zicheng Ling ,  Steven Young

    发明人： Xiao-Jie Yuan ,  Michael Hart ,  Zicheng Ling ,  Steven Young

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.