公开(公告)号：US06996661B2

公开(公告)日：2006-02-07

申请号：US10615923

申请日：2003-07-10

Applicant: Masami Hasegawa ,  Yoichi Satoh ,  Yuuji Yanagisawa ,  Yoshio Iioka ,  Yoshimi Kitagawa ,  Makio Uchida

Inventor： Masami Hasegawa ,  Yoichi Satoh ,  Yuuji Yanagisawa ,  Yoshio Iioka ,  Yoshimi Kitagawa ,  Makio Uchida

IPC: G06F12/00

CPC classification number: G11C7/1075 ,  G06F13/1689 ,  Y02D10/14

Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.

公开(公告)号：US06625686B2

公开(公告)日：2003-09-23

申请号：US10214124

申请日：2002-08-08

Applicant: Masami Hasegawa ,  Yoichi Satoh ,  Yuuji Yanagisawa ,  Yoshio Iioka ,  Yoshimi Kitagawa ,  Makio Uchida

Inventor： Masami Hasegawa ,  Yoichi Satoh ,  Yuuji Yanagisawa ,  Yoshio Iioka ,  Yoshimi Kitagawa ,  Makio Uchida

IPC: G06F1200

CPC classification number: G11C7/1075 ,  G06F13/1689 ,  Y02D10/14

Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.

公开(公告)号：US06480947B1

公开(公告)日：2002-11-12

申请号：US09353367

申请日：1999-07-15

Applicant: Masami Hasegawa ,  Yoichi Satoh ,  Yuuji Yanagisawa ,  Yoshio Iioka ,  Yoshimi Kitagawa ,  Makio Uchida

Inventor： Masami Hasegawa ,  Yoichi Satoh ,  Yuuji Yanagisawa ,  Yoshio Iioka ,  Yoshimi Kitagawa ,  Makio Uchida

IPC: G06F1200

CPC classification number: G11C7/1075 ,  G06F13/1689 ,  Y02D10/14

Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.

Abstract translation: 多端口存储器具有电连接到RAM的访问端口的多个RAM和端口扩展单元。 端口扩展单元包括：输入电路，其允许用于每个存储周期并行地激活RAM的访问控制信息，以通过多个存储周期共同输入;定时发生器，其产生能够串行地规定每个存储周期的内部时钟信号 时钟信号（ck）的一个周期的逻辑电路，以及逻辑电路，其能够在与内部时钟信号同步的每个串行存储器循环中以部分顺序地将输入到输入电路的访问控制信息并行地分配给多个RAM。 端口扩展单元允许访问具有多个RAM的访问端口作为单个多端口存储器。

公开(公告)号：US5317537A

公开(公告)日：1994-05-31

申请号：US888493

申请日：1992-05-27

Applicant: Satoshi Shinagawa ,  Yoichi Sato ,  Masami Hasegawa ,  Yasushi Shimono ,  Masayuki Miyasaka ,  Takatoshi Tamura ,  Yoshio Iioka

Inventor： Satoshi Shinagawa ,  Yoichi Sato ,  Masami Hasegawa ,  Yasushi Shimono ,  Masayuki Miyasaka ,  Takatoshi Tamura ,  Yoshio Iioka

IPC: G11C11/41 ,  G11C7/14 ,  G11C8/16 ,  H04Q3/52 ,  H04Q11/04 ,  G11C13/00

CPC classification number: G11C7/14 ,  G11C8/16

Abstract: A multi-port memory device has a memory cell array including one or more memory blocks each of which has a plurality of memory cells arranged in rows and columns, and a plurality of dummy cells, with one dummy cell being provided for each row of memory cells in each of the memory blocks so that the dummy cells are connected with associated ones of the word lines extending in the row direction. The dummy cells are further connected with dummy cell bit lines extending in the column direction. Sense amplifiers are connected to receive outputs of those memory cells in the memory cell array which are selected in a memory cell selection operation and outputs of those dummy cells among the plurality of dummy cells which are selected in the memory cell selection operation for amplifying differences between the selected memory cell outputs and the selected dummy cell outputs. Precharging and shielding arrangements are also provided for improved operation.

Abstract translation: 多端口存储器件具有包括一个或多个存储器块的存储单元阵列，每个存储块具有以行和列排列的多个存储器单元，以及多个虚设单元，每个存储器行提供一个虚拟单元 每个存储器块中的单元，使得虚设单元与在行方向上延伸的字线相关联地连接。 虚拟单元进一步与在列方向上延伸的虚拟单元位线连接。 连接感测放大器以接收在存储单元选择操作中选择的存储单元阵列中的这些存储单元的输出，并且在存储单元选择操作中选择的多个虚设单元中的这些虚设单元的输出， 所选择的存储单元输出和所选择的虚拟单元输出。 还提供了预充电和屏蔽装置，以改善操作。