公开(公告)号：US07541292B2

公开(公告)日：2009-06-02

申请号：US11414027

申请日：2006-04-28

申请人： Kallol Bera ,  Xiaoye Zhao ,  Kenny L. Doan ,  Ezra Robert Gold ,  Paul Lukas Brillhart ,  Bruno Geoffrion ,  Bryan Pu ,  Daniel J. Hoffman

发明人： Kallol Bera ,  Xiaoye Zhao ,  Kenny L. Doan ,  Ezra Robert Gold ,  Paul Lukas Brillhart ,  Bruno Geoffrion ,  Bryan Pu ,  Daniel J. Hoffman

IPC分类号： H01L21/461

CPC分类号： H01L21/76802 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/3266 ,  H01J37/32706 ,  H01J2237/3347 ,  H01L21/31116

摘要： A plasma etch process for etching high aspect ratio openings in a dielectric film on a workpiece is carried out in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a first polymerizing etch process gas through a radially inward one of plural concentric gas injection zones in the ceiling electrode and injecting a second polymerizing etch process gas through a radially outward one of the plural concentric gas injection zones in the ceiling electrode, the compositions of the first and second process gases having first and second carbon-to-fluorine ratios that differ from one another. The process further includes evacuating gas from the reactor through a pumping annulus surrounding an edge of the workpiece, and etching the high aspect ratio openings in the dielectric film with etch species derived from the etch process gas while depositing a polymer derived from the etch process gas onto the workpiece, by generating a plasma in the reactor.

摘要翻译： 用于蚀刻工件上的电介质膜中的高纵横比开口的等离子体蚀刻工艺在具有覆盖工件的顶部电极的反应器和支撑工件的静电卡盘上进行。 该方法包括将第一聚合蚀刻工艺气体通过天花板电极中的多个同心气体注入区的径向向内的一个注入，并且通过天花板电极中的多个同心气体注入区中的径向向外的一个喷射第二聚合蚀刻工艺气体， 第一和第二工艺气体的组成具有彼此不同的第一和第二碳 - 氟比率。 该方法还包括通过围绕工件边缘的泵送环空将气体从反应器排出，以及用蚀刻工艺气体衍生的蚀刻物质蚀刻电介质膜中的高纵横比开口，同时沉积衍生自蚀刻工艺气体的聚合物 通过在反应器中产生等离子体而在工件上。

公开(公告)号：US07435685B2

公开(公告)日：2008-10-14

申请号：US11531493

申请日：2006-09-13

申请人： Gerardo A. Delgadino ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

发明人： Gerardo A. Delgadino ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

IPC分类号： H01L21/311

CPC分类号： H01L21/76826 ,  H01L21/76811 ,  H01L21/76813

摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

摘要翻译： 一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。

公开(公告)号：US20080050922A1

公开(公告)日：2008-02-28

申请号：US11508345

申请日：2006-08-23

申请人： Hairong Tang ,  Xiaoye Zhao ,  Keiji Horioka ,  Jeremiah T. P. Pender

发明人： Hairong Tang ,  Xiaoye Zhao ,  Keiji Horioka ,  Jeremiah T. P. Pender

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L21/31116 ,  H01J37/32862

摘要： A chamber dry cleaning process particularly useful after a dielectric plasma etch process which exposes an underlying copper metallization. After the dielectric etch process, the production wafer is removed from the chamber and a cleaning gas is excited into a plasma to clean the chamber walls and recover the dielectric etching characteristic of the chamber. Preferably, the cleaning gas is reducing such as hydrogen gas with the addition of nitrogen gas. Alternatively, the cleaning gas may an oxidizing gas. If the wafer pedestal is vacant during the cleaning, it is not electrically biased. If a dummy wafer is placed on the pedestal during cleaning, the pedestal is biased. The cleaning process is advantageously performed every wafer cycle.

摘要翻译： 在暴露下面的铜金属化的电介质等离子体蚀刻工艺之后，室干燥方法特别有用。 在电介质蚀刻工艺之后，将生产晶片从腔室中取出，将清洁气体激发到等离子体中以清洁腔室壁并恢复腔室的介电蚀刻特性。 优选地，通过添加氮气，清洁气体如氢气还原。 或者，清洁气体可以是氧化气体。 如果晶片基座在清洁过程中空出，则不会电气偏置。 如果在清洁时将底座放置在基座上，则基座偏置。 有利地，每个晶片周期执行清洁处理。

公开(公告)号：US07309448B2

公开(公告)日：2007-12-18

申请号：US10706902

申请日：2003-11-12

申请人： Hee Yeop Chae ,  Jeremiah T. P. Pender ,  Gerardo A. Delgadino ,  Xiaoye Zhao ,  Yan Ye

发明人： Hee Yeop Chae ,  Jeremiah T. P. Pender ,  Gerardo A. Delgadino ,  Xiaoye Zhao ,  Yan Ye

IPC分类号： B44C1/22 ,  H01L21/302

CPC分类号： H01L21/76808 ,  H01L21/31116

摘要： A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.

摘要翻译： 使用等离子体蚀刻室中的气体混合物的等离子体在衬底上在介电材料（例如碳掺杂氧化物）上选择性地蚀刻牺牲光吸收材料（SLAM）的工艺。 气体混合物包括氢氟烃气体，任选的含氢气体，任选的富氟碳氟化合物气体，氮气，氧气和惰性气体。 该方法可以提供大于10:1的介电材料蚀刻选择比的SLAM。

公开(公告)号：US07256134B2

公开(公告)日：2007-08-14

申请号：US10632873

申请日：2003-08-01

申请人： Yunsang Kim ,  Neungho Shin ,  Heeyeop Chae ,  Joey Chiu ,  Yan Ye ,  Fang Tian ,  Xiaoye Zhao

发明人： Yunsang Kim ,  Neungho Shin ,  Heeyeop Chae ,  Joey Chiu ,  Yan Ye ,  Fang Tian ,  Xiaoye Zhao

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  Y10S438/963

摘要： The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 Å/min.

摘要翻译： 本发明包括使用等离子体蚀刻室中的气体混合物的等离子体来选择性地蚀刻形成在衬底上的低k电介质材料的方法。 气体混合物包括富氟碳氟化合物或氢氟烃气体，含氮气体和一种或多种添加剂气体，例如富氢氢氟烃气体，惰性气体和/或碳 - 氧气体。 该方法提供了大于约5:1的光致抗蚀剂掩模蚀刻选择比的低k电介质，大于10:1的低k电介质到阻挡层/衬层蚀刻选择比，以及低k电介质蚀刻速率 高于约4000Å/ min。

公开(公告)号：US07132618B2

公开(公告)日：2006-11-07

申请号：US10359989

申请日：2003-02-06

申请人： Daniel J. Hoffman ,  Yan Ye ,  Dan Katz ,  Douglas A. Buchberger, Jr. ,  Xiaoye Zhao ,  Kang-Lie Chiang ,  Robert B. Hagen ,  Matthew L. Miller

发明人： Daniel J. Hoffman ,  Yan Ye ,  Dan Katz ,  Douglas A. Buchberger, Jr. ,  Xiaoye Zhao ,  Kang-Lie Chiang ,  Robert B. Hagen ,  Matthew L. Miller

IPC分类号： B23K9/00

CPC分类号： H01J37/3244 ,  H01J37/32082 ,  H01J37/32183 ,  H01J37/3266

摘要： A plasma reactor for processing a semiconductor workpiece, includes reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

公开(公告)号：US08048806B2

公开(公告)日：2011-11-01

申请号：US11372752

申请日：2006-03-10

申请人： Michael C. Kutney ,  Daniel J. Hoffman ,  Gerardo A. Delgadino ,  Ezra R. Gold ,  Ashok Sinha ,  Xiaoye Zhao ,  Douglas H. Burns ,  Shawming Ma

发明人： Michael C. Kutney ,  Daniel J. Hoffman ,  Gerardo A. Delgadino ,  Ezra R. Gold ,  Ashok Sinha ,  Xiaoye Zhao ,  Douglas H. Burns ,  Shawming Ma

IPC分类号： H01L21/00 ,  H01L21/302 ,  G01L21/30

CPC分类号： H01L21/67069 ,  H01L21/31116 ,  H01L21/76807

摘要： In some implementations, a method is provided in a plasma processing chamber for stabilizing etch-rate distributions during a process transition from one process step to another process step. The method includes performing a pre-transition compensation of at least one other process parameter so as to avoid unstable plasma states by inhibiting formation of a parasitic plasma during the process transition. In some implementations, a method is provided for processing a workpiece in plasma processing chamber, which includes inhibiting deviations from an expected etch-rate distribution by avoiding unstable plasma states during a process transition from one process step to another process step.

摘要翻译： 在一些实施方案中，在等离子体处理室中提供了一种方法，用于在从一个处理步骤到另一个处理步骤的过程转变期间稳定蚀刻速率分布。 该方法包括执行至少一个其它过程参数的预过渡补偿，以便通过在过程转换期间抑制寄生等离子体的形成来避免不稳定的等离子体状态。 在一些实施方案中，提供了一种用于处理等离子体处理室中的工件的方法，其包括通过在从一个工艺步骤转换到另一工艺步骤的过程转变期间避免不稳定的等离子体状态来抑制预期蚀刻速率分布的偏差。

公开(公告)号：US20080145998A1

公开(公告)日：2008-06-19

申请号：US11531493

申请日：2006-09-13

申请人： GERARDO A. DELGADINO ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

发明人： GERARDO A. DELGADINO ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

IPC分类号： H01L21/76

CPC分类号： H01L21/76826 ,  H01L21/76811 ,  H01L21/76813

摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

摘要翻译： 一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔是 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。

公开(公告)号：US07186943B2

公开(公告)日：2007-03-06

申请号：US11105307

申请日：2005-04-12

申请人： Daniel J. Hoffman ,  Yan Ye ,  Dan Katz ,  Douglas A. Buchberger, Jr. ,  Xiaoye Zhao ,  Kang-Lie Chiang ,  Robert B. Hagen ,  Matthew L. Miller

发明人： Daniel J. Hoffman ,  Yan Ye ,  Dan Katz ,  Douglas A. Buchberger, Jr. ,  Xiaoye Zhao ,  Kang-Lie Chiang ,  Robert B. Hagen ,  Matthew L. Miller

IPC分类号： B23K10/06

CPC分类号： H01J37/3244 ,  H01J37/32082 ,  H01J37/32183 ,  H01J37/3266

摘要： A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

摘要翻译： 一种用于处理半导体工件的等离子体反应器，包括具有室壁并具有用于保持半导体支撑件的工件支撑件的反应室，所述电极包括室壁的一部分，RF发电机，用于以 发电机到顶置电极并且能够将室内的等离子体保持在期望的等离子体离子密度水平。 顶置电极具有这样的电容，使得在期望的等离子体离子密度下在室中形成的顶置电极和等离子体以电极 - 等离子体共振频率共振，发电机的频率至少接近电极 - 等离子体共振频率。 反应器还包括围绕晶片表面的等离子体处理区域的一组MERIE磁体，其产生缓慢循环的磁场，其搅动等离子体以改善等离子体离子密度分布均匀性。

公开(公告)号：US07132369B2

公开(公告)日：2006-11-07

申请号：US10745344

申请日：2003-12-22

申请人： Gerardo A. Delgadino ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

发明人： Gerardo A. Delgadino ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

IPC分类号： H01L21/302

CPC分类号： H01L21/76826 ,  H01L21/76811 ,  H01L21/76813

摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

摘要翻译： 一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。