公开(公告)号：US20140313626A1

公开(公告)日：2014-10-23

申请号：US13867034

申请日：2013-04-20

Applicant: Xiaobao Wang

Inventor： Xiaobao Wang

IPC: H02H9/04

CPC classification number: H02H9/04 ,  H02H7/1222 ,  H02H7/1227 ,  H02M1/32 ,  H02M3/1582

Abstract: A programmable system includes a first level protection circuit comprised of discharge tube CR1/CR2 and piezoresistor MOV1/MOV2 in series; a second-level protection circuit comprised of the series arm of capacitor C1 and resistor R1 in parallel with a transient voltage suppression diode TVS1, and inductors L1/L2 connected to the ends of first level and second-level protection circuits respectively. A control circuit includes a PWM driver module and a SCM. The PWM driver module is connected to the PWM control port of the SCM and its output is connected to an IGBT module. The control circuit is also connected to a series communication module and to a user interface. The features of the invention are: strong-shock resistance; a wide range of load adaptability; and ability of accurately and steplessly regulating and adjusting with high frequency and high power load.

Abstract translation: 可编程系统包括串联的放电管CR1 / CR2和压控电阻MOV1 / MOV2组成的第一电平保护电路; 包括电容器C1的串联臂和与瞬态电压抑制二极管TVS1并联的电阻器R1的二级保护电路，以及分别连接到第一级和第二级保护电路两端的电感器L1 / L2。 控制电路包括PWM驱动器模块和SCM。 PWM驱动器模块连接到SCM的PWM控制端口，其输出连接到IGBT模块。 控制电路还连接到串行通信模块和用户接口。 本发明的特点是：抗冲击性强; 适应范围广泛; 以及高频，高功率负载下精确，无级调节调节的能力。

公开(公告)号：US08854078B1

公开(公告)日：2014-10-07

申请号：US13223989

申请日：2011-09-01

Applicant: Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

Inventor： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

IPC: H03K17/16

CPC classification number: H04L25/0298 ,  H04L25/0278

Abstract: Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

Abstract translation: 用于动态控制源和端接阻抗的电路，方法和装置。 一个输出级在发送时提供串联终止，并在接收数据时提供并行终止。 当输出级将引脚从低电压拉到高电平时，上拉器件的标称阻抗为50欧姆，而当引脚从高电压拉出时，下拉器件的标称阻抗为50欧姆 到低电压。 上拉和下拉设备在接收数据时都打开。 由于其非线性电流 - 电压特性，当引脚电压高于电源电压的一半时，上拉器件显示为50欧姆，而当引脚电压低于50欧姆时，下拉器件显示为50欧姆 电源电压的一半。 可以校准上拉和下拉器件以提供标称的50欧姆阻抗。

公开(公告)号：US08384460B1

公开(公告)日：2013-02-26

申请号：US13420349

申请日：2012-03-14

Applicant: Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

Inventor： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

IPC: H03H11/16

CPC classification number: H03L7/0814 ,  H03K2005/00293

Abstract: An adjustable delay circuit includes first and second transistors each having a control input coupled to an input node of the adjustable delay circuit and an output coupled to an output node of the adjustable delay circuit. The adjustable delay circuit includes a first pass gate coupled between first and second capacitors and the output node of the adjustable delay circuit. The first and the second capacitors are coupled between a node at a high voltage and a node at a low voltage. The first pass gate is operable to be controlled by a first delay control signal.

Abstract translation: 可调延迟电路包括第一和第二晶体管，每个晶体管具有耦合到可调延迟电路的输入节点的控制输入和耦合到可调延迟电路的输出节点的输出。 可调延迟电路包括耦合在第一和第二电容器之间的第一通过栅极和可调延迟电路的输出节点。 第一和第二电容器耦合在高电压节点和低电压节点之间。 第一通过门可操作以由第一延迟控制信号控制。

公开(公告)号：US08149038B1

公开(公告)日：2012-04-03

申请号：US12729114

申请日：2010-03-22

Applicant: Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

Inventor： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

IPC: H03H11/16

CPC classification number: H03L7/0814 ,  H03K2005/00293

Abstract: A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic input signals. A multiplexer circuit selects a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals. A phase detection circuit compares a phase of the selected periodic signal to a data signal to generate a phase detection signal. A control logic circuit generates the select signals. The control logic circuit adjusts the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal.

Abstract translation: 动态相位对准电路包括具有产生周期性输出信号的延迟锁定环路电路的相位发生器电路。 每个延迟锁定环路电路响应于至少两个周期性输入信号产生周期性输出信号之一。 多路复用器电路基于选择信号从周期性输入信号和周期性输出信号中选择选定的周期信号。 相位检测电路将选择的周期信号的相位与数据信号进行比较，以产生相位检测信号。 控制逻辑电路产生选择信号。 控制逻辑电路基于相位检测信号的变化来调整选择信号，以使多路复用器电路调整所选周期信号的相位。

公开(公告)号：US08022723B1

公开(公告)日：2011-09-20

申请号：US11458675

申请日：2006-07-19

Applicant: Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

Inventor： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

IPC: H03K17/16

CPC classification number: H04L25/0298 ,  H04L25/0278

Abstract: Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

Abstract translation: 用于动态控制源和端接阻抗的电路，方法和装置。 一个输出级在发送时提供串联终止，并在接收数据时提供并行终止。 当输出级将引脚从低电压拉到高电平时，上拉器件的标称阻抗为50欧姆，而当引脚从高电压拉出时，下拉器件的标称阻抗为50欧姆 到低电压。 上拉和下拉设备在接收数据时都打开。 由于其非线性电流 - 电压特性，当引脚电压高于电源电压的一半时，上拉器件显示为50欧姆，而当引脚电压低于50欧姆时，下拉器件显示为50欧姆 电源电压的一半。 可以校准上拉和下拉器件以提供标称的50欧姆阻抗。

公开(公告)号：US20070236247A1

公开(公告)日：2007-10-11

申请号：US11381356

申请日：2006-05-02

Applicant: Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

Inventor： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

IPC: H03K17/16

CPC classification number: G11C7/1048 ,  G11C2207/2254 ,  H03H11/30 ,  H04L25/0278 ,  H04L25/0292

Abstract: On-chip termination (OCT)calibration techniques are provided that support input/output (IO) banks on an integrated circuit (IC) using OCT controllers. The OCT controllers calibrate the on-chip termination impedance in the IO banks using a shared parallel bus or separate parallel buses. Multiplexers or select logic in each IO bank select control signals from the OCT controllers in response to select signals. According to some embodiments, each of the IO banks on an IC can receive OCT control signals from any of the OCT controllers on the IC.

Abstract translation: 提供使用OCT控制器在集成电路（IC）上支持输入/输出（IO）组的片上终止（OCT）校准技术。 OCT控制器使用共享并行总线或单独的并行总线校准IO组中的片上终端阻抗。 每个IO组中的多路复用器或选择逻辑根据选择信号选择来自OCT控制器的控制信号。 根据一些实施例，IC上的每个IO组可以从IC上的任何OCT控制器接收OCT控制信号。

公开(公告)号：US07221193B1

公开(公告)日：2007-05-22

申请号：US11040048

申请日：2005-01-20

Applicant: Xiaobao Wang ,  Tzung-Chin Chang ,  Chiakang Sung ,  Khai Q. Nguyen

Inventor： Xiaobao Wang ,  Tzung-Chin Chang ,  Chiakang Sung ,  Khai Q. Nguyen

IPC: H03B1/00

CPC classification number: H03K19/0005 ,  H04L25/0298

Abstract: Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using calibration circuits. Each calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When the effective resistance of the group of transistors matches the external resistance, the calibration circuit causes the effective resistance of drive transistors in the IO buffer to match the effective resistance of the group of on-chip transistors.

Abstract translation: 提供了使用校准电路来控制输入或输出（IO）缓冲器中的片上终端电阻的技术。 每个校准电路监视外部电阻和片上晶体管组之间的电压。 当晶体组的有效电阻与外部电阻相匹配时，校准电路使得IO缓冲器中的驱动晶体管的有效电阻与片上晶体管组的有效电阻相匹配。

公开(公告)号：US07215143B1

公开(公告)日：2007-05-08

申请号：US11000472

申请日：2004-11-29

Applicant: Jonathan Chung ,  In Whan Kim ,  Philip Pan ,  Chiakang Sung ,  Bonnie Wang ,  Xiaobao Wang ,  Yan Chong ,  Gopinath Rangan ,  Khai Nguyen ,  Tzung-Chin Chang ,  Joseph Huang

Inventor： Jonathan Chung ,  In Whan Kim ,  Philip Pan ,  Chiakang Sung ,  Bonnie Wang ,  Xiaobao Wang ,  Yan Chong ,  Gopinath Rangan ,  Khai Nguyen ,  Tzung-Chin Chang ,  Joseph Huang

IPC: H03K19/094 ,  H03K19/0948 ,  H03K17/00

CPC classification number: H03K19/018585

Abstract: An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

Abstract translation: 输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。 例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。 一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

公开(公告)号：US06970024B1

公开(公告)日：2005-11-29

申请号：US10786370

申请日：2004-02-24

Applicant: Dirk Reese ,  Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Gopinath Rangan ,  Xiaobao Wang

Inventor： Dirk Reese ,  Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Gopinath Rangan ,  Xiaobao Wang

IPC: H03K3/01 ,  H03K3/356 ,  H03K19/003

CPC classification number: H03K3/356113 ,  H03K19/00315

Abstract: Circuits, methods, and apparatus for protecting devices in an output stage from over-voltage conditions caused by high supply and input voltages. Embodiments provide over-voltage protection that operates over a range of voltage levels, and that can be optimized for performance at different voltage levels. An exemplary embodiment of the present invention uses stacked devices to protect n and p-channel output devices from excess supply and input voltages. These stacked devices are biased by voltages received at their gates. These gate voltages vary as a function of supply voltage to maintain performance. Other embodiments of the present invention provide a body bias switch that generates a bias for the bulk of p-channel output devices. This bias tracks the higher of a supply or input voltage, such that parasitic drain-to-bulk diodes do not conduct. A switch may be provided that shorts the bulk connection to VCC under appropriate conditions.

Abstract translation: 用于保护输出级的器件免受由高电源和输入电压引起的过电压状态的电路，方法和装置。 实施例提供了在一定范围的电压电平上工作的过电压保护，并且可针对不同电压电平下的性能进行优化。 本发明的示例性实施例使用堆叠器件来保护n和p沟道输出器件免受过多的电源和输入电压的影响。 这些堆叠的器件被其栅极处接收的电压偏置。 这些栅极电压随着电源电压而变化，以保持性能。 本发明的其它实施例提供一种主体偏置开关，其产生用于大量p沟道输出装置的偏置。 该偏置跟踪电源或输入电压的较高，使得寄生漏极 - 体二极管不导通。 可以提供在适当条件下短路与VCC的大容量连接的开关。

公开(公告)号：US06853215B1

公开(公告)日：2005-02-08

申请号：US10685355

申请日：2003-10-09

Applicant: Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

Inventor： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

IPC: C07K14/47 ,  C07K16/28 ,  H03K19/173

CPC classification number: C07K16/28 ,  A61K2039/505 ,  C07K14/47

Abstract: A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed 110 modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

Abstract translation: 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速110模式（例如双数据速率和零总线周转）进行操作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块向输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。