公开(公告)号：US07002405B2

公开(公告)日：2006-02-21

申请号：US10777629

申请日：2004-02-13

申请人： Todd Brooks ,  Jungwoo Song ,  Wynstan Tong

发明人： Todd Brooks ,  Jungwoo Song ,  Wynstan Tong

IPC分类号： G05G7/12 ,  G05G7/26

CPC分类号： H03F3/45183 ,  H03F2203/45352 ,  H03F2203/45356 ,  H03F2203/45392 ,  H03F2203/45396 ,  H03F2203/45504 ,  H03F2203/45648 ,  H03F2203/45696 ,  H03F2203/7203 ,  H03K5/2481

摘要： A low noise transconductance cell includes a resistor and a differential circuit pair having two equivalent half-circuits. Each half-circuit includes a feedback loop coupled to the resistor. The feedback loop includes an input transistor coupled to an inverting gain stage. The inverting gain stage is coupled to an output transistor which in turn is coupled to the input transistor and the resistor. In a low noise transconductance cell, a bias current source is coupled to the center of series connected resistors. In a high swing transconductance cell, a first bias current source is coupled to the left terminal of a resistance stage and a second bias current source is coupled to the right terminal of the resistance stage. The resistance stage can include a single resistor or a plurality of resistors.

摘要翻译： 低噪声跨导单元包括具有两个等效半电路的电阻器和差分电路对。 每个半电路包括耦合到电阻器的反馈回路。 反馈回路包括耦合到反相增益级的输入晶体管。 反相增益级耦合到输出晶体管，输出晶体管又连接到输入晶体管和电阻器。 在低噪声跨导电池中，偏置电流源耦合到串联电阻的中心。 在高摆幅跨导单元中，第一偏置电流源耦合到电阻级的左端，第二偏置电流源耦合到电阻级的右端。 电阻级可以包括单个电阻器或多个电阻器。

公开(公告)号：US07623050B2

公开(公告)日：2009-11-24

申请号：US11637801

申请日：2006-12-13

申请人： Michael Le ,  Chun-Ying Chen ,  Wynstan Tong ,  Kwang Young Kim ,  Hui Pan

发明人： Michael Le ,  Chun-Ying Chen ,  Wynstan Tong ,  Kwang Young Kim ,  Hui Pan

IPC分类号： H03M1/06

CPC分类号： H03M1/1023 ,  H03M1/363

摘要： A method and apparatus to counter effects of an offset voltage by calibrating an analog-to-digital converter (ADC). A digital calibration loop minimizes the effects of offset voltage to improve ADC accuracy as well as provide a low-power, submicron-scale ADC. A calibration circuit senses an ADC output and adjusts a variable calibration voltage to counter the effects of the offset voltage. Reduction of the offset voltage effects increases the ADC accuracy.

摘要翻译： 通过校准模数转换器（ADC）来抵消偏移电压的影响的方法和装置。 数字校准环路可以最大限度地减少偏移电压的影响，从而提高ADC精度，同时提供低功耗，亚微米级的ADC。 校准电路检测ADC输出，并调整可变校准电压以抵消偏移电压的影响。 降低失调电压的影响会增加ADC精度。

公开(公告)号：US20070152863A1

公开(公告)日：2007-07-05

申请号：US11637801

申请日：2006-12-13

申请人： Michael Le ,  Chun-Ying Chen ,  Wynstan Tong ,  Kwang Kim ,  Hui Pan

发明人： Michael Le ,  Chun-Ying Chen ,  Wynstan Tong ,  Kwang Kim ,  Hui Pan

IPC分类号： H03M1/12

CPC分类号： H03M1/1023 ,  H03M1/363

摘要： A method and apparatus to counter effects of an offset voltage by calibrating an analog-to-digital converter (ADC). A digital calibration loop minimizes the effects of offset voltage to improve ADC accuracy as well as provide a low-power, submicron-scale ADC. A calibration circuit senses an ADC output and adjusts a variable calibration voltage to counter the effects of the offset voltage. Reduction of the offset voltage effects increases the ADC accuracy.

摘要翻译： 通过校准模数转换器（ADC）来抵消偏移电压的影响的方法和装置。 数字校准环路可以最大限度地减少偏移电压的影响，从而提高ADC精度，同时提供低功耗，亚微米级的ADC。 校准电路检测ADC输出，并调整可变校准电压以抵消偏移电压的影响。 降低失调电压的影响会增加ADC精度。