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    On current in one-time-programmable memory cells
    1.
    发明授权
    On current in one-time-programmable memory cells 有权
    关于一次可编程存储单元中的电流

    公开(公告)号：US08679929B2

    公开(公告)日：2014-03-25

    申请号：US13312304

    申请日：2011-12-06

    申请人： Shanjen “Robert” Pan ,  Allan T. Mitchell ,  Weidong Tian

    发明人： Shanjen “Robert” Pan ,  Allan T. Mitchell ,  Weidong Tian

    IPC分类号： H01L21/336 ,  H01L21/425

    CPC分类号： H01L21/28273 ,  H01L27/11206 ,  H01L27/11233 ,  H01L29/66825 ,  H01L29/7885

    摘要： A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.

    摘要翻译： 一种在其编程状态之一制造具有改进的读取电流的一次性可编程（OTP）存储单元的方法，以及如此制造的存储单元。 OTP存储单元的侧面由沟槽隔离结构构成。 在沟槽蚀刻之后，并且在用介电材料填充隔离沟槽之前，在沟槽表面中执行氟注入。 植入物可能垂直于装置表面或与法线成一角度。 然后完成单元晶体管以形成浮栅金属氧化物半导体（MOS）晶体管。 来自氟植入物的改进的导通电流（Ion）。

    On Current in One-Time-Programmable Memory Cells
    2.
    发明申请
    On Current in One-Time-Programmable Memory Cells 有权
    关于一次性可编程存储器单元中的电流

    公开(公告)号：US20130143375A1

    公开(公告)日：2013-06-06

    申请号：US13312304

    申请日：2011-12-06

    申请人： Shanjen "Robert" Pan ,  Allan T. Mitchell ,  Weidong Tian

    发明人： Shanjen "Robert" Pan ,  Allan T. Mitchell ,  Weidong Tian

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  H01L27/11206 ,  H01L27/11233 ,  H01L29/66825 ,  H01L29/7885

    摘要： A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.

    摘要翻译： 一种在其编程状态之一制造具有改进的读取电流的一次可编程（OTP）存储单元的方法，以及如此制造的存储器单元。 OTP存储单元的侧面由沟槽隔离结构构成。 在沟槽蚀刻之后，并且在用介电材料填充隔离沟槽之前，在沟槽表面中执行氟注入。 植入物可能垂直于装置表面或与法线成一角度。 然后完成单元晶体管以形成浮栅金属氧化物半导体（MOS）晶体管。 来自氟植入物的改进的导通电流（Ion）。

    VERSATILE SYSTEM FOR CHARGE DISSIPATION IN THE FORMATION OF SEMICONDUCTOR DEVICE STRUCTURES
    3.
    发明申请
    VERSATILE SYSTEM FOR CHARGE DISSIPATION IN THE FORMATION OF SEMICONDUCTOR DEVICE STRUCTURES 有权
    用于形成半导体器件结构的充电放电的多元系统

    公开(公告)号：US20070057247A1

    公开(公告)日：2007-03-15

    申请号：US11468648

    申请日：2006-08-30

    申请人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    发明人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    IPC分类号： H01L31/00

    CPC分类号： H01L27/0248 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.

    摘要翻译： 本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏 。 衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。 第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。 第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。 在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。 第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。

    VERSATILE SYSTEM FOR CHARGE DISSIPATION IN THE FORMATION OF SEMICONDUCTOR DEVICE STRUCTURES
    4.
    发明申请
    VERSATILE SYSTEM FOR CHARGE DISSIPATION IN THE FORMATION OF SEMICONDUCTOR DEVICE STRUCTURES 有权
    用于形成半导体器件结构的充电放电的多元系统

    公开(公告)号：US20060214170A1

    公开(公告)日：2006-09-28

    申请号：US11420922

    申请日：2006-05-30

    申请人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    发明人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0248 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.

    摘要翻译： 本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏 。 衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。 第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。 第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。 在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。 第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。

    Versatile system for charge dissipation in the formation of semiconductor device structures
    5.
    发明申请
    Versatile system for charge dissipation in the formation of semiconductor device structures 有权

    公开(公告)号：US20060033173A1

    公开(公告)日：2006-02-16

    申请号：US10917763

    申请日：2004-08-13

    申请人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    发明人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    IPC分类号： H01L29/76 ,  H01L31/062

    CPC分类号： H01L27/0248 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.

    Current in one-time-programmable memory cells
    6.
    发明授权
    Current in one-time-programmable memory cells 有权
    一次可编程存储单元中的电流

    公开(公告)号：US08664706B2

    公开(公告)日：2014-03-04

    申请号：US13528250

    申请日：2012-06-20

    申请人： Shanjen “Robert” Pan ,  Allan T. Mitchell ,  Weidong Tian

    发明人： Shanjen “Robert” Pan ,  Allan T. Mitchell ,  Weidong Tian

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L21/28273 ,  H01L27/11206 ,  H01L27/11233 ,  H01L29/66825 ,  H01L29/7885

    摘要： A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.

    摘要翻译： 一种在其编程状态之一制造具有改进的读取电流的一次可编程（OTP）存储单元的方法，以及如此制造的存储单元。 OTP存储单元的侧面由沟槽隔离结构构成。 在沟槽蚀刻之后，并且在用介电材料填充隔离沟槽之前，在沟槽表面中执行氟注入。 植入物可能垂直于装置表面或与法线成一角度。 然后完成单元晶体管以形成浮栅金属氧化物半导体（MOS）晶体管。 来自氟植入物的改进的导通电流（Ion）。

    Fluorine Implant Under Isolation Dielectric Structures to Improve Bipolar Transistor Performance and Matching
    7.
    发明申请
    Fluorine Implant Under Isolation Dielectric Structures to Improve Bipolar Transistor Performance and Matching 有权
    氟植入物隔离电介质结构提高双极晶体管性能和匹配

    公开(公告)号：US20130065374A1

    公开(公告)日：2013-03-14

    申请号：US13451355

    申请日：2012-04-19

    申请人： Weidong Tian ,  Ming-Yeh Chuang ,  Rajni J. Aggarwal

    发明人： Weidong Tian ,  Ming-Yeh Chuang ,  Rajni J. Aggarwal

    IPC分类号： H01L21/331

    CPC分类号： H01L29/732 ,  H01L29/1004 ,  H01L29/66272

    摘要： A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch.

    摘要翻译： 一种制造包括双极晶体管的集成电路的方法，其降低了等离子体蚀刻期间由充电引起的晶体管性能下降和晶体管失配的影响，以及如此形成的集成电路。 在形成隔离电介质之前，在要形成基极和发射极之间的隔离电介质结构的那些位置处进行氟注入。 隔离电介质结构可以通过浅沟槽隔离来形成，其中氟注入在沟槽蚀刻之后进行，或LOCOS氧化，其中氟注入在热氧化之前进行。 氟注入可以垂直于器件表面或与法线成一定角度。 然后执行集成电路的完成，包括使用需要等离子体蚀刻的相对厚的铜金属化。

    Versatile system for charge dissipation in the formation of semiconductor device structures
    8.
    发明授权
    Versatile system for charge dissipation in the formation of semiconductor device structures 有权
    用于形成半导体器件结构的电荷耗散的通用系统

    公开(公告)号：US07592252B2

    公开(公告)日：2009-09-22

    申请号：US11468648

    申请日：2006-08-30

    申请人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    发明人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/0248 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.

    摘要翻译： 本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏 。 衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。 第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。 第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。 在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。 第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。