公开(公告)号：US20140040692A1

公开(公告)日：2014-02-06

申请号：US13567512

申请日：2012-08-06

Applicant: Dharin N. Shah ,  Sharad Gupta ,  Vinod Joseph Menezes ,  Vish Visvanathan

Inventor： Dharin N. Shah ,  Sharad Gupta ,  Vinod Joseph Menezes ,  Vish Visvanathan

IPC: G06F11/26

CPC classification number: G11C29/021 ,  G06F11/24 ,  G11C29/44 ,  G11C2029/0409

Abstract: Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example.

Abstract translation: 可能由操作逻辑和/或存储器电路在不足的工作电压引起的潜在的错误通过电子改变复制或操作电路的节点来识别，使得电改变的节点容易出错。 使用参数驱动器控制实施例中的电改变的节点。 可以通过在边缘工作电压下操作并检测例如检测电气改变的节点中的错误的电压阈值来选择最小化的工作电压。

公开(公告)号：US09158683B2

公开(公告)日：2015-10-13

申请号：US13571343

申请日：2012-08-09

Applicant: Aman A Kokrady ,  Shahid Ali ,  Vish Visvanathan ,  Vinod Joseph Menezes

Inventor： Aman A Kokrady ,  Shahid Ali ,  Vish Visvanathan ,  Vinod Joseph Menezes

IPC: G06F12/06 ,  G11C8/16

CPC classification number: G06F12/06 ,  G11C8/16 ,  Y02D10/13

Abstract: A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.

Abstract translation: 多端口存储器仿真器在一个操作时钟周期中接收用于并行处理存储器命令的第一和第二存储器命令。 数据操作数存储在排列为行和存储体的位单元的存储器阵列中。 辅助存储体提供用于物理存储每行的附加字的比特单元。 第一和第二存储器命令中的每一个的存储体地址部分分别被转换为第一和第二物理存储体地址。 响应于银行地址部分相等的确定并且与第一银行地址相关联的银行被指定为用于随后接收的存储器命令的当前未使用的存储体，第二物理存储体地址被分配当前未使用的存储体的存储体地址 响应于银行地址部分相等的确定。 可以同时进行读写操作。

公开(公告)号：US08762804B2

公开(公告)日：2014-06-24

申请号：US13567512

申请日：2012-08-06

Applicant: Dharin N Shah ,  Sharad Gupta ,  Vinod Joseph Menezes ,  Vish Visvanathan

Inventor： Dharin N Shah ,  Sharad Gupta ,  Vinod Joseph Menezes ,  Vish Visvanathan

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G11C29/021 ,  G06F11/24 ,  G11C29/44 ,  G11C2029/0409

Abstract: Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example.

Abstract translation: 可能由操作逻辑和/或存储器电路在不足的工作电压引起的潜在的错误通过电子改变复制或操作电路的节点来识别，使得电改变的节点容易出错。 使用参数驱动器控制实施例中的电改变的节点。 可以通过在边缘工作电压下操作并检测例如检测电气改变的节点中的错误的电压阈值来选择最小化的工作电压。

公开(公告)号：US20140047197A1

公开(公告)日：2014-02-13

申请号：US13571343

申请日：2012-08-09

Applicant: Aman A. Kokrady ,  Shahid Ali ,  Vish Visvanathan ,  Vinod Joseph Menezes

Inventor： Aman A. Kokrady ,  Shahid Ali ,  Vish Visvanathan ,  Vinod Joseph Menezes

IPC: G06F12/00

CPC classification number: G06F12/06 ,  G11C8/16 ,  Y02D10/13

Abstract: A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.

Abstract translation: 多端口存储器仿真器在一个操作时钟周期中接收用于并行处理存储器命令的第一和第二存储器命令。 数据操作数存储在排列为行和存储体的位单元的存储器阵列中。 辅助存储体提供用于物理存储每行的附加字的比特单元。 第一和第二存储器命令中的每一个的存储体地址部分分别被转换为第一和第二物理存储体地址。 响应于银行地址部分相等的确定并且与第一银行地址相关联的银行被指定为用于随后接收的存储器命令的当前未使用的存储体，第二物理存储体地址被分配当前未使用的存储体的存储体地址 响应于银行地址部分相等的确定。 可以同时进行读写操作。