公开(公告)号：US6060349A

公开(公告)日：2000-05-09

申请号：US152449

申请日：1998-09-14

Applicant: Tzu-Min Peng ,  Keh-Ching Huang ,  Tung-Po Chen ,  Tz-Guei Jung

Inventor： Tzu-Min Peng ,  Keh-Ching Huang ,  Tung-Po Chen ,  Tz-Guei Jung

IPC: H01L21/8242

CPC classification number: H01L27/10844 ,  H01L27/10852

Abstract: A planarization method used in fabricating an embedded dynamic random access memory (DRAM). After a number of metal-oxide semiconductor (MOS) transistors and a number of capacitors are formed on a semiconductor substrate, a first inter-layer di-electric (ILD) layer is formed over the substrate. The embedded DRAM is divided into a memory region and a logic region. Next, planarization is performed. A dummy metal layer is formed and coupled to an interchangeable source/drain region of the MOS transistor in the logic region. Then a second ILD layer is formed over the logic region to compensate difference in height between the logic region and the memory region. Then, a via hole/plug is formed in the logic region to extend the first metal layer. A second metal layer with required contact window/plugs is formed over the substrate.

Abstract translation: 用于制造嵌入式动态随机存取存储器（DRAM）的平面化方法。 在半导体衬底上形成多个金属氧化物半导体（MOS）晶体管和多个电容器之后，在衬底上形成第一层间二电极（ILD）层。 嵌入式DRAM被分成存储区域和逻辑区域。 接下来，进行平坦化。 形成虚设的金属层并与逻辑区域中的MOS晶体管的可互换的源/漏区耦合。 然后在逻辑区域上形成第二ILD层以补偿逻辑区域和存储区域之间的高度差异。 然后，在逻辑区域中形成通孔/插头以延伸第一金属层。 在衬底上形成具有所需接触窗/插塞的第二金属层。

公开(公告)号：US5731243A

公开(公告)日：1998-03-24

申请号：US523775

申请日：1995-09-05

Applicant: Tzu-min Peng ,  Yung-Haw Liaw ,  Cheng-Te Chu ,  Hsin-chieh Huang

Inventor： Tzu-min Peng ,  Yung-Haw Liaw ,  Cheng-Te Chu ,  Hsin-chieh Huang

IPC: H01L21/304 ,  H01L21/306 ,  H01L23/485 ,  H01L21/28 ,  H01L21/3065

CPC classification number: H01L21/02046 ,  H01L21/304 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/85013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/14

Abstract: A method for backside grinding a semiconductor wafer and forming a contamination free bonding pad connection. The method comprises forming a passivation layer over a metal layer. Applying a photoresist pattern with an opening which will define a bonding pad area and removing the passivation layer exposed in the opening. Next, the photoresist is removed, but a polymer residue is often formed on the surfaces of the passivation layer surrounding the bonding pad. In a novel step, the residue is removed using an etchant containing Dimethylsulfoxide (D.M.D.O.) aud Monoethanolamine (M.E.A.) and is followed by au oxygen plasma treatment. Next, the device side of the wafer is covered with a protective tape and the backside of the wafer is grouud back. The tape is removed revealing a contamination free bonding pad area. A bonding connection is then made to the bonding pad.

Abstract translation: 一种用于背面研磨半导体晶片并形成无污染的焊盘连接的方法。 该方法包括在金属层上形成钝化层。 施加具有开口的光致抗蚀剂图案，其将限定接合焊盘区域并去除暴露在开口中的钝化层。 接下来，去除光致抗蚀剂，但是通常在包围焊盘的钝化层的表面上形成聚合物残渣。 在新的步骤中，使用含有二甲基亚砜（D.M.D.O.）的单乙醇胺（M.E.A.）的蚀刻剂除去残余物，然后进行氧氧等离子体处理。 接下来，晶片的器件侧被保护带覆盖，并且晶片的背面被覆盖。 去除胶带，露出无污染的焊盘区域。 然后对接合焊盘进行接合连接。

公开(公告)号：US5672543A

公开(公告)日：1997-09-30

申请号：US639677

申请日：1996-04-29

Applicant: Chaur Rong Chang ,  Po-Tao Chu ,  Tzu-Min Peng ,  Kuang-Hui Chang

Inventor： Chaur Rong Chang ,  Po-Tao Chu ,  Tzu-Min Peng ,  Kuang-Hui Chang

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/76843 ,  H01L21/76877 ,  Y10S438/937

Abstract: A new method of metallization using a tungsten plug is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer covers the semiconductor device structures wherein a contact opening is made through the insulating layer to the semiconductor substrate. A barrier layer is deposited conformally over the surface of the insulating layer and within the contact opening. A stress buffer layer is deposited overlying the barrier layer wherein the stress buffer layer prevents volcano defects. A tungsten plug is formed within the contact opening to complete the formation of the tungsten plug metallization without volcano defects in the fabrication of an integrated circuit device.

Abstract translation: 描述了使用钨丝塞的新的金属化方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 绝缘层覆盖其中通过绝缘层到半导体衬底的接触开口的半导体器件结构。 保护层在绝缘层的表面和接触开口内共形沉积。 沉积在阻挡层上的应力缓冲层，其中应力缓冲层防止火山缺陷。 在接触开口中形成钨插塞，以在集成电路器件的制造中完成钨插塞金属化的形成而没有火山缺陷。

公开(公告)号：US5604134A

公开(公告)日：1997-02-18

申请号：US597493

申请日：1996-02-02

Applicant: Kuan-Hui Chang ,  Tzu-Min Peng ,  Po-Tao Chu ,  Shin-Kuei Yen

Inventor： Kuan-Hui Chang ,  Tzu-Min Peng ,  Po-Tao Chu ,  Shin-Kuei Yen

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/12

Abstract: Plasma reactors are used extensively in the manufacture of integrated circuits for the deposition and etching of thin films at low temperatures. Their range of operating temperatures and gas pressures make them highly susceptible to build-up of deposits on the inner surfaces of the reaction chamber which subsequently become dislodged by vibrations, stresses, and other aggravations and are dispersed within the system as particulates. The monitoring of particulate accumulation on wafers is conventionally done by subjecting a test wafer to a simulated operation within the tool under gas flow alone. Some types of plasma reactors incorporate oscillating gas dispersion housings in order to improve homogeneity of the gas mixture. The motion of these housings can induce significant particle displacement within the chamber. The correct monitoring procedure for these tools must therefore include the motion of the distribution housing in addition to the conventional procedures.

Abstract translation: 等离子体反应器广泛用于制造用于低温沉积和蚀刻薄膜的集成电路。 它们的工作温度和气体压力范围使得它们非常容易在反应室的内表面上积累，随后由于振动，应力和其它恶化而被移除，并作为颗粒分散在系统内。 通常，通过在单独的气体流下使试验晶片在工具内进行模拟操作来进行对晶片上的颗粒积聚的监测。 一些类型的等离子体反应器包括振荡气体分散壳体，以改善气体混合物的均匀性。 这些壳体的运动可以在室内引起显着的颗粒位移。 因此，这些工具的正确监控程序除了常规程序外，还必须包括配电箱的运动。

公开(公告)号：US06316368B1

公开(公告)日：2001-11-13

申请号：US09286080

申请日：1999-04-05

Applicant: Kwang-Ming Lin ,  Tzu-Min Peng ,  Chieh-Te Chen ,  Pang-Miao Liu

Inventor： Kwang-Ming Lin ,  Tzu-Min Peng ,  Chieh-Te Chen ,  Pang-Miao Liu

IPC: H01L21302

CPC classification number: H01L21/31144 ,  H01L21/0332 ,  H01L21/76804 ,  H01L21/76838

Abstract: A method of fabricating a node contact opening is described. A dielectric layer is formed on a substrate. A first conductive layer is formed on the dielectric layer. The first conductive layer is etched to form a trapezoidally cross-sectioned opening exposing a portion of the dielectric layer. The dielectric layer exposed by the trapezoidally cross-sectioned opening is etched to form a node contact opening in the dielectric layer exposing a part the substrate. A second conductive layer is formed to fill the node contact opening and in contact with the conductive layer.

Abstract translation: 描述了制造节点接触开口的方法。 在基板上形成电介质层。 在介电层上形成第一导电层。 蚀刻第一导电层以形成暴露电介质层的一部分的梯形截面的开口。 蚀刻由梯形截面的开口暴露的电介质层，以在电介质层中形成露出衬底部分的节点接触开口。 形成第二导电层以填充节点接触开口并与导电层接触。