Twin MONOS array for high speed application
    1.
    发明申请
    Twin MONOS array for high speed application 有权
    双MONOS阵列用于高速应用

    公开(公告)号:US20080186763A1

    公开(公告)日:2008-08-07

    申请号:US12079966

    申请日:2008-03-31

    CPC classification number: G11C16/08 G11C16/0466 G11C16/16 H01L29/792

    Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

    Abstract translation: 双MONOS金属位阵列的字栅和控制栅的针迹区域配置包括在字门的侧壁上的控制栅极,其中字栅和控制栅并联运行。 控制栅极多晶硅触点在垂直于控制栅极的针脚区域处接触排列成一排的控制栅极。 缝合区域的两个字门多晶硅接点交替字门。 还提供了位线,字线和控制门解码器和驱动器,位线解码器,位线控制电路和用于控制存储器阵列的芯片控制器。 本发明还提供双MONOS金属位阵列操作,其包括由一个控制栅极驱动电路驱动的多个控制栅极和由一个字栅极驱动器电路驱动的一个字栅极以及擦除禁止和块擦除。

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