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1.发明授权Use of robbed framing bits to provide secondary pots channel over extended range ISDN communications network 有权使用抢劫的位位置在扩展范围的ISDN通信网络上提供二级通道公开(公告)号：US06519267B1
公开(公告)日：2003-02-11
申请号：US09351082
申请日：1999-07-09
IPC分类号： A04J312
CPC分类号： H04J3/172 , H04Q11/0428 , H04Q2213/13034 , H04Q2213/1309 , H04Q2213/13094 , H04Q2213/13174 , H04Q2213/13209 , H04Q2213/13216
摘要： The currently defined industry standard framing structure for 2B1Q ISDN signaling, at 160 kilobaud, provides 128 kbps for a customer (B1, B2) data channel, and 16 kbps for a data (D) channel. Of the remaining 16 kbps non payload bandwidth, 4 kbps are used for overhead maintenance data. Eight kbps of the remaining 12 kbps of non payload bandwidth, that customarily transport a repeated framing pattern, are usurped for the transport of an auxiliary compressed (from 64 KHz to 8 KHz) digitized voice POTS channel, that is sufficient to transport toll quality voice. The remaining framing pattern bandwidth is adequate prevent an unacceptable reduction in bit error rate.
摘要翻译： 目前定义的行业标准框架结构，用于2BiQ ISDN信令（160千比特），为客户（B1，B2）数据信道提供128kbps，对于数据（D）信道提供16kbps。 在剩余的16 kbps非有效载荷带宽中，4 kbps用于架空维护数据。 剩余的12kbps的非有效载荷带宽的8kbps（通常传输重复的帧模式）被用于传输辅助压缩（从64KHz到8KHz）的数字化语音POTS信道，这足以传输费用质量语音 。 剩余的帧模式带宽足以防止误码率的不可接受的降低。
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公开(公告)号：US06728649B2
公开(公告)日：2004-04-27
申请号：US10061848
申请日：2002-02-01
IPC分类号： H03B100
CPC分类号： H03K5/1252
摘要： A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output. Thus, the present invention removes glitches from a received clock signal and outputs a glitch-free clock signal.
摘要翻译： 本发明提供一种从时钟信号中去除毛刺，干扰或噪声的方法和装置。 根据本发明，监视毛刺时钟信号以确定何时发生毛刺时钟信号中的转变。 当发生转变时，根据第二高速时钟信号启动计数器。 该计数器的值与比较值进行比较。 比较值被选择为近似等于毛刺时钟信号的期望周期。 如果计数器值等于比较值，则假定转换是有效的转换，并且转换被传送并作为无毛刺时钟信号输出。 然而，如果在计数值等于计数器比较值之前发生转换，则假设转换无效，并且没有转移到无毛刺时钟输出。 因此，本发明从接收的时钟信号中去除毛刺，并输出无毛刺的时钟信号。
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3.发明授权Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications 失效减少脉冲填充同步数字通信中等待时间抖动的方法和装置
公开(公告)号：US5680422A
公开(公告)日：1997-10-21
申请号：US429951
申请日：1995-04-27
CPC分类号： H04J3/073
摘要： A wander reduction mechanism in an HDSL pulse-stuffing synchronization system provides a more precise measure of the phase of the incoming asynchronous signal than is obtained in conventional schemes, in which the only information available is the presence or absence of stuffing pulses. An auxiliary phase comparator and phase adjuster are incorporated into the synchronizer-multiplexer to generate a reference data clock (derived from the synchronized data clock), so that the incoming unsynchronized data clock can be tracked. As the clock is iteratively phase-adjusted, the respective changes are accumulated. At the end of a prescribed measurement interval, the net contents of the accumulator are encoded and transported over the synchronous digital data communication channel to the receiver. By decoding this sequence information, the desynchronizer is able to generate a desynchronized data clock having the same number of net phase adjustments during a measurement period as the reference clock at the synchronizer.
摘要翻译： 在HDSL脉冲填充同步系统中的漫游减少机制提供了比传统方案中获得的输入异步信号的相位更精确的测量，其中唯一可用的信息是填充脉冲的存在或不存在。 辅助相位比较器和相位调节器被并入到同步器多路复用器中以产生参考数据时钟（从同步数据时钟导出），使得可以跟踪输入的不同步的数据时钟。 随着时钟被迭代地相位调整，各个变化被累积。 在规定的测量间隔结束时，累加器的净内容被编码并通过同步数字数据通信信道传送到接收机。 通过对该序列信息进行解码，去同步器能够在测量周期期间产生具有相同数量的净相位调整的去同步数据时钟作为同步器处的参考时钟。
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