公开(公告)号：US10904200B2

公开(公告)日：2021-01-26

申请号：US16380556

申请日：2019-04-10

申请人： Talla, Inc.

发明人： Byron Galbraith ,  Jon Klein

IPC分类号： H04L29/02 ,  H04L12/58 ,  G06N20/00 ,  G06F9/54 ,  G06Q30/02 ,  G06Q10/10 ,  G06F40/30

摘要： Systems, apparatus, and methods are disclosed for intelligent communication over multiple communications platforms. A dispatch controller interfaces with at least one communication platform to obtain and convert messages to a platform-agnostic format annotated with user and source information. A processing and routing controller applies natural language processing and machine learning techniques to interpret user requests and simultaneously become better at interpreting user requests. A task performance controller invokes specific tasks extracted from routed messages and/or initiates responses to user requests. At least one message bus communicates between the dispatch controller, the processing controller, and the task performance controller, and at least one memory device stores data and processor-executable instructions employed by the dispatch controller, the processing controller, and the task performance controller.

公开(公告)号：US20190306107A1

公开(公告)日：2019-10-03

申请号：US16380556

申请日：2019-04-10

申请人： Talla, Inc.

发明人： Byron GALBRAITH ,  Jon KLEIN

IPC分类号： H04L12/58 ,  G06F9/54 ,  G06N20/00 ,  G06F17/27

摘要： Systems, apparatus, and methods are disclosed for intelligent communication over multiple communications platforms. A dispatch controller interfaces with at least one communication platform to obtain and convert messages to a platform-agnostic format annotated with user and source information. A processing and routing controller applies natural language processing and machine learning techniques to interpret user requests and simultaneously become better at interpreting user requests. A task performance controller invokes specific tasks extracted from routed messages and/or initiates responses to user requests. At least one message bus communicates between the dispatch controller, the processing controller, and the task performance controller, and at least one memory device stores data and processor-executable instructions employed by the dispatch controller, the processing controller, and the task performance controller.