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    Semiconductor memory device having fixed CAS latency in normal operation and various CAS latencies in test mode
    2.
    发明授权
    Semiconductor memory device having fixed CAS latency in normal operation and various CAS latencies in test mode 失效
    半导体存储器件在正常操作中具有固定的CAS延迟和测试模式下的各种CAS延迟

    公开(公告)号：US06392909B1

    公开(公告)日：2002-05-21

    申请号：US09818876

    申请日：2001-03-27

    Applicant: Tae-seong Jang ,  Tae-jin Yoo

    Inventor： Tae-seong Jang ,  Tae-jin Yoo

    IPC: G11C700

    CPC classification number: G11C8/18 ,  G11C29/14

    Abstract: A semiconductor memory device having a fixed CAS latency during a normal operation and various CAS latencies during a test mode. The semiconductor memory device a master signal generator for generating a master signal in response to a power-up signal and a latency test signal. A plurality of fuse information units generate fuse information signals in response to the power-up signal and the master signal. A plurality of mode register set (MRS) address information units receive address bits during an interval where an address window signal is activated to generate MRS address latch signals in response to a MRS addressing signal. A CAS latency determining unit generates CAS latency select signals in response to the fuse information signals and the MRS address latch signals, wherein the CAS latency select signals provide a fixed CAS latency during a normal mode of operation of the semiconductor device and varying CAS latencies during a test mode of operation of the semiconductor device.

    Abstract translation: 在正常操作期间具有固定CAS延迟并且在测试模式期间具有各种CAS延迟的半导体存储器件。 半导体存储器件，主信号发生器，用于响应于上电信号和等待时间测试信号产生主信号。 多个熔丝信息单元响应上电信号和主信号产生熔丝信息信号。 多个模式寄存器组（MRS）地址信息单元在地址窗口信号被激活的间隔期间接收地址位，以响应于MRS寻址信号而产生MRS地址锁存信号。 CAS等待时间确定单元响应于熔丝信息信号和MRS地址锁存信号产生CAS等待时间选择信号，其中CAS等待时间选择信号在半导体器件的正常工作模式期间提供固定的CAS延迟并且改变CAS延迟 半导体器件的测试操作模式。

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