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公开(公告)号：US20060126388A1
公开(公告)日：2006-06-15
申请号：US11274483
申请日：2005-11-16
申请人： Edvin Paparisto , Stephan Rogl
发明人： Edvin Paparisto , Stephan Rogl
IPC分类号： G11C16/06
CPC分类号： G11C29/1201 , G11C16/04 , G11C29/50 , G11C29/50004 , G11C2029/5006
摘要： The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and delivering an analog current signal generated during the mirroring, or an analog current signal derived from it, to an analog output pad of a memory component.
摘要翻译： 本发明涉及用于测量存储单元电流的程序和装置，特别是用于非易失性存储器组件的装置，其中该装置具有用于在读取存储单元时流过存储单元的电流的电流镜像装置， 在镜像期间产生的模拟电流信号或从其导出的模拟电流信号到存储器组件的模拟输出焊盘。
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2.发明授权公开(公告)号：US07236403B2
公开(公告)日：2007-06-26
申请号：US11005804
申请日：2004-12-07
IPC分类号： G11C16/00
摘要： Precharge arrangement for read access for integrated nonvolatile memories having at least one memory cell (2), at least one source line (8), at least one bit line (9), at least one sense amplifier (3) and at least one precharge potential, the bit line (9) continuously having the precharge potential in a deselected state of the bit line (9), and the source line (8) having a predetermined reference potential, in particular a ground potential (10), in a selected state of the bit line (9).
摘要翻译： 用于具有至少一个存储器单元（2），至少一个源极线（8），至少一个位线（9），至少一个读出放大器（3）和至少一个预充电的集成非易失性存储器的读取访问的预充电布置 电位，位线（9）连续地具有处于位线（9）的取消选择状态的预充电电位，以及具有预定参考电位的源极线（8），特别是接地电位（10） 位线（9）的状态。
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公开(公告)号：US20050030085A1
公开(公告)日：2005-02-10
申请号：US10888323
申请日：2004-07-09
申请人： Maciej Jankowski , Stephan Rogl
发明人： Maciej Jankowski , Stephan Rogl
IPC分类号： H03K17/06 , H03K17/687
CPC分类号： H03K17/063
摘要： The present invention provides a method for actuating a transistor (10) having the following steps: (a) a first predetermined positive potential is applied to a first voltage supply node (13) in a latch circuit (11), the voltage supply node (13) being coupled to a control connection on the transistor (10); (b) a reference-ground potential is applied to a second voltage supply node (14) in the latch circuit (11), the second voltage supply node (14) being connected to a source connection on the transistor (10); (c) the latch circuit (11) is set to a predetermined state, which turns the transistor (10) on or off; (d) the potential at the second voltage supply node (14) is lowered; and (e) the potential at the first voltage supply node (13) is lowered if the potential difference between the first and second voltage supply nodes (13, 14) exceeds a predetermined threshold value.
摘要翻译： 本发明提供一种用于致动晶体管（10）的方法，具有以下步骤：（a）第一预定正电位施加到锁存电路（11）中的第一电压供应节点（13），电压供应节点 13）耦合到晶体管（10）上的控制连接; （b）参考地电位施加到锁存电路（11）中的第二电压供应节点（14），第二电压供应节点（14）连接到晶体管（10）上的源极连接; （c）锁存电路（11）被设定为预定状态，使晶体管（10）接通或断开; （d）第二电压供给节点（14）的电位降低; 和（e）如果第一和第二电压供应节点（13,14）之间的电位差超过预定阈值，则第一电压供应节点（13）处的电位降低。
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4.发明申请Device to be used for reading out a memory cell, and method for reading out a memory cell 有权用于读出存储单元的装置，以及读出存储单元的方法公开(公告)号：US20060280008A1
公开(公告)日：2006-12-14
申请号：US11444696
申请日：2006-06-01
申请人： Edvin Paparisto , Stephan Rogl
发明人： Edvin Paparisto , Stephan Rogl
IPC分类号： G11C29/00
CPC分类号： G11C7/12
摘要： A method for reading out a memory cell, and a device to be used for reading out a memory cell is disclosed. In one embodiment, the device includes a first circuit and a second circuit for regulating a voltage present at a line that is adapted to be connected with the memory cell to a predetermined value (Uref), wherein said first circuit includes a switching element, and wherein said first circuit is configured such that said switching element is switched on during a first regulating phase and is switched off during a second regulating phase.
摘要翻译： 公开了一种用于读出存储单元的方法和用于读出存储单元的装置。 在一个实施例中，该装置包括第一电路和第二电路，用于将适于与存储器单元连接的线路上存在的电压调节到预定值（U SUB ref），其中所述 第一电路包括开关元件，并且其中所述第一电路被配置为使得所述开关元件在第一调节阶段期间被接通，并且在第二调节阶段期间被切断。
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5.发明申请公开(公告)号：US20050128813A1
公开(公告)日：2005-06-16
申请号：US11005804
申请日：2004-12-07
摘要： Precharge arrangement for read access for integrated nonvolatile memories having at least one memory cell (2), at least one source line (8), at least one bit line (9), at least one sense amplifier (3) and at least one precharge potential, the bit line (9) continuously having the precharge potential in a deselected state of the bit line (9), and the source line (8) having a predetermined reference potential, in particular a ground potential (10), in a selected state of the bit line (9).
摘要翻译： 用于具有至少一个存储器单元（2），至少一个源极线（8），至少一个位线（9），至少一个读出放大器（3）和至少一个预充电的集成非易失性存储器的读取访问的预充电布置 电位，位线（9）连续地具有处于位线（9）的取消选择状态的预充电电位，以及具有预定参考电位的源极线（8），特别是接地电位（10） 位线（9）的状态。
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6.发明授权Device for reading out a memory cell including a regulating circuit with parallel switching elements, and method 有权用于读出包括具有并联开关元件的调节电路的存储单元的装置及方法公开(公告)号：US07548474B2
公开(公告)日：2009-06-16
申请号：US11444696
申请日：2006-06-01
申请人： Edvin Paparisto , Stephan Rogl
发明人： Edvin Paparisto , Stephan Rogl
IPC分类号： G11C7/00
CPC分类号： G11C7/12
摘要： A method for reading out a memory cell, and a device to be used for reading out a memory cell. In one embodiment, the device includes a first circuit and a second circuit for regulating a voltage present at a line that is adapted to be connected with the memory cell to a predetermined value, wherein said first circuit includes a switching element, and wherein said first circuit is configured such that said switching element is switched on during a first regulating phase and is switched off during a second regulating phase.
摘要翻译： 用于读出存储单元的方法，以及用于读出存储单元的装置。 在一个实施例中，该装置包括第一电路和第二电路，用于将存在于适于与存储器单元连接的线路上的电压调节到预定值，其中所述第一电路包括开关元件，并且其中所述第一 电路被配置为使得所述开关元件在第一调节阶段期间接通并且在第二调节阶段期间被切断。
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公开(公告)号：US07379339B2
公开(公告)日：2008-05-27
申请号：US11274483
申请日：2005-11-16
申请人： Edvin Paparisto , Stephan Rogl
发明人： Edvin Paparisto , Stephan Rogl
CPC分类号： G11C29/1201 , G11C16/04 , G11C29/50 , G11C29/50004 , G11C2029/5006
摘要： The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and delivering an analog current signal generated during the mirroring, or an analog current signal derived from it, to an analog output pad of a memory component.
摘要翻译： 本发明涉及用于测量存储单元电流的程序和装置，特别是用于非易失性存储器组件的装置，其中该装置具有用于在读取存储单元时流过存储单元的电流的电流镜像装置， 在镜像期间产生的模拟电流信号或从其导出的模拟电流信号到存储器组件的模拟输出焊盘。
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公开(公告)号：US07042249B2
公开(公告)日：2006-05-09
申请号：US10888323
申请日：2004-07-09
申请人： Maciej Jankowski , Stephan Rogl
发明人： Maciej Jankowski , Stephan Rogl
IPC分类号： H03K3/356
CPC分类号： H03K17/063
摘要： The present invention provides a method for actuating a transistor (10) having the following steps: (a) a first predetermined positive potential is applied to a first voltage supply node (13) in a latch circuit (11), the voltage supply node (13) being coupled to a control connection on the transistor (10); (b) a reference-ground potential is applied to a second voltage supply node (14) in the latch circuit (11), the second voltage supply node (14) being connected to a source connection on the transistor (10); (c) the latch circuit (11) is set to a predetermined state, which turns the transistor (10) on or off; (d) the potential at the second voltage supply node (14) is lowered; and (e) the potential at the first voltage supply node (13) is lowered if the potential difference between the first and second voltage supply nodes (13, 14) exceeds a predetermined threshold value.
摘要翻译： 本发明提供了一种用于致动晶体管（10）的方法，具有以下步骤：（a）第一预定正电位施加到锁存电路（11）中的第一电压供应节点（13），电压供应节点 13）耦合到晶体管（10）上的控制连接; （b）参考地电位施加到锁存电路（11）中的第二电压供应节点（14），第二电压供应节点（14）连接到晶体管（10）上的源极连接; （c）锁存电路（11）被设定为预定状态，使晶体管（10）接通或断开; （d）第二电压供给节点（14）的电位降低; 和（e）如果第一和第二电压供应节点（13,14）之间的电位差超过预定阈值，则第一电压供应节点（13）处的电位降低。
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