公开(公告)号：US4115796A

公开(公告)日：1978-09-19

申请号：US784715

申请日：1977-04-05

申请人： Takeo Fujimoto ,  Yasuo Torimaru ,  Shin-ichi Ogawa ,  Shinya Yasue

发明人： Takeo Fujimoto ,  Yasuo Torimaru ,  Shin-ichi Ogawa ,  Shinya Yasue

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L27/04

CPC分类号： H01L27/088 ,  H01L27/0927

摘要： Formation of well-regions of a conductivity type opposite to that of a substrate is achieved in such a manner to determine a first threshold voltage level. Ion implantation is effected on desirably selected gates in the respective channels formed on the substrate and the well-regions. Two channels on the ion implanted substrate and on the well-region in which the ion implantation is not effected, are coupled to form a complementary-MOS transistor pair having a first threshold voltage level. The channels on the substrate in which the ion implantation is not effected and on the ion implanted well-region are coupled to form another complementary-MOS transistor pair having a second threshold voltage level.

摘要翻译： 以确定第一阈值电压电平的方式实现与基板的导电类型相反的导电类型的阱区的形成。 在形成在衬底和阱区上的相应沟道中的期望选择的栅极上实现离子注入。 离子注入基板上的两个通道和不影响离子注入的阱区被耦合以形成具有第一阈值电压电平的互补MOS晶体管对。 不影响离子注入的衬底上的通道和离子注入的阱区被耦合以形成具有第二阈值电压电平的另一个互补MOS晶体管对。