公开(公告)号：US08588013B2

公开(公告)日：2013-11-19

申请号：US13336840

申请日：2011-12-23

申请人： Shin Ho Chu

发明人： Shin Ho Chu

IPC分类号： G11C7/00

CPC分类号： G11C8/18 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/18

摘要： A semiconductor memory device includes: a strobe clock generator configured to generate a strobe clock signal having a delay time controlled according to a plurality of test mode signals which are selectively enabled in response to a read signal or write signal; an internal address generator configured to latch an address in response to a first level of the strobe clock signal, and generate an internal address by decoding the address in response to a second level of the strobe clock signal; and an output enable signal generator configured to decode the internal address and generate output enable signals which are selectively enabled.

摘要翻译： 半导体存储器件包括：选通时钟发生器，被配置为产生具有根据多个测试模式信号控制的延迟时间的选通时钟信号，所述测试模式信号响应于读取信号或写入信号被选择性地使能; 内部地址发生器，被配置为响应于所述选通时钟信号的第一电平来锁存地址，并且响应于所述选通时钟信号的第二电平对所述地址进行解码来产生内部地址; 以及输出使能信号发生器，被配置为对内部地址进行解码并产生有选择地使能的输出使能信号。

公开(公告)号：US20130114358A1

公开(公告)日：2013-05-09

申请号：US13336840

申请日：2011-12-23

申请人： Shin Ho CHU

发明人： Shin Ho CHU

IPC分类号： G11C8/18

CPC分类号： G11C8/18 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/18

摘要： A semiconductor memory device includes: a strobe clock generator configured to generate a strobe clock signal having a delay time controlled according to a plurality of test mode signals which are selectively enabled in response to a read signal or write signal; an internal address generator configured to latch an address in response to a first level of the strobe clock signal, and generate an internal address by decoding the address in response to a second level of the strobe clock signal; and an output enable signal generator configured to decode the internal address and generate output enable signals which are selectively enabled.

摘要翻译： 半导体存储器件包括：选通时钟发生器，被配置为产生具有根据多个测试模式信号控制的延迟时间的选通时钟信号，所述测试模式信号响应于读取信号或写入信号被选择性地使能; 内部地址发生器，被配置为响应于所述选通时钟信号的第一电平来锁存地址，并且响应于所述选通时钟信号的第二电平对所述地址进行解码来产生内部地址; 以及输出使能信号发生器，被配置为对内部地址进行解码并产生有选择地使能的输出使能信号。

公开(公告)号：US20100142299A1

公开(公告)日：2010-06-10

申请号：US12704674

申请日：2010-02-12

申请人： Shin Ho CHU ,  Sun Mo AN

发明人： Shin Ho CHU ,  Sun Mo AN

IPC分类号： G11C29/00 ,  G11C17/18

CPC分类号： G11C17/18 ,  G11C17/165 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/785 ,  G11C2229/763

摘要： In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled.

摘要翻译： 在反熔丝修复控制电路中，将半导体存储器件集成到多芯片封装中以进行抗熔丝修复。 反熔丝修复控制电路包括数据掩模信号输入电路，单元地址使能单元，修复使能单元和修复单元。 数据屏蔽信号输入电路在接收到用于反熔丝修复的测试控制信号时，接收并输出数据屏蔽信号。 单元地址使能单元接收到反熔丝修复地址，以便在接收到从数据屏蔽信号输入电路输出的数据屏蔽信号时，使反熔丝单元的单元地址能够被修复。 修复使能单元根据是否启用与单元地址对应的反熔丝单元，对单元地址进行编码并输出修复使能信号和驱动信号。 当修复使能信号，地址和驱动信号被使能时，维修单元向反熔丝单元提供修复电压。

公开(公告)号：US20100032669A1

公开(公告)日：2010-02-11

申请号：US12483372

申请日：2009-06-12

申请人： Sun Mo AN ,  Shin Ho CHU

发明人： Sun Mo AN ,  Shin Ho CHU

IPC分类号： H01L23/58

CPC分类号： G11C29/46

摘要： A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state.

摘要翻译： 提出了能够控制测试模式而不停止半导体集成电路测试的半导体集成电路。 半导体集成电路包括：测试模式控制单元，被配置为响应于地址解码信号产生第一组的多个测试模式信号和第二组的多个测试模式信号。 测试模式控制单元通过使用第二组的测试模式信号提供复位信号来选择性地使第一组的测试模式信号失效。 因此，可以通过使用复位信号使先前的测试模式失效并且通过执行新的测试模式而不断开测试模式状态来减少半导体集成电路的测试时间。

公开(公告)号：US20090168840A1

公开(公告)日：2009-07-02

申请号：US12317218

申请日：2008-12-18

申请人： Ho Uk Song ,  Shin Ho Chu

发明人： Ho Uk Song ,  Shin Ho Chu

IPC分类号： G01K7/00

CPC分类号： G01K3/005

摘要： A temperature data output circuit is provided which is capable of outputting a temperature signal which is enabled when an internal temperature of at least one of the semiconductor memory chips mounted on a multi chip package exceeds a predetermined temperature.

摘要翻译： 提供温度数据输出电路，其能够输出当安装在多芯片封装上的至少一个半导体存储器芯片的内部温度超过预定温度时使能的温度信号。

公开(公告)号：US20090059691A1

公开(公告)日：2009-03-05

申请号：US12169594

申请日：2008-07-08

申请人： Shin Ho Chu ,  Jong Won Lee

发明人： Shin Ho Chu ,  Jong Won Lee

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/18 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/2602

摘要： A semiconductor integrated circuit includes a multi-mode control signal generating section that enables one of up and down mat input/output switch control signals for controlling input/output switches in up and down mats according to up/down information addresses during a read operation mode, a multi-mode decoding section that simultaneously activates multi mat selection signals corresponding to one of the up mats and one of the down mats according to row addresses in an active operation mode, and a mat control section that receives the up and down mat input/output switch control signals and the multi mat selection signals and enables word lines and input/output switches in the mats corresponding to the signals.

摘要翻译： 半导体集成电路包括多模式控制信号产生部分，其能够在读操作模式期间根据上/下信息地址使得上和下输入/输出开关控制信号之一用于根据上/下信息地址来控制上/下按钮中的输入/输出开关 ，多模式解码部分，其根据活动操作模式中的行地址同时激活对应于上层和下层之一的多层选择信号;以及垫控制部分，其接收上和下垫输入 /输出开关控制信号和多功能席选择信号，并使得字符线和输入/输出开关在与信号相对应的垫中。

公开(公告)号：US20080123460A1

公开(公告)日：2008-05-29

申请号：US11811863

申请日：2007-06-11

申请人： Shin Ho Chu

发明人： Shin Ho Chu

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C5/144

摘要： A deep power down mode control circuit is disclosed. The deep power down mode control circuit includes a deep power down signal generator for outputting a deep power down signal in response to a burst command signal and a clock enable signal, and a deep power down delay controller for delaying the deep power down signal for a predetermined delay time, and outputting the delayed signal.

摘要翻译： 公开了一种深度掉电模式控制电路。 深度掉电模式控制电路包括深度掉电信号发生器，用于响应于突发命令信号和时钟使能信号输出深度掉电信号，以及深度掉电延迟控制器，用于将深度掉电信号延迟用于 预定的延迟时间，并输出延迟的信号。

公开(公告)号：US20080101134A1

公开(公告)日：2008-05-01

申请号：US12000956

申请日：2007-12-19

申请人： Shin-Ho Chu

发明人： Shin-Ho Chu

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4068

摘要： Disclosed herein is a self refresh control device for reducing a current leakage of transistors in off-state. The apparatus for controlling a voltage used in a semiconductor memory device includes a first voltage supplying block for supplying a first voltage to the semiconductor memory device in response to an inputted control signal; and a second voltage supplying block for supplying a second voltage to the semiconductor memory device in response to the inputted control signal, wherein the first and the second voltages are used as a bulk voltage of a transistor included in the semiconductor memory device.

摘要翻译： 这里公开了一种用于减少截止状态下的晶体管的电流泄漏的自刷新控制装置。 用于控制半导体存储器件中使用的电压的装置包括：第一电压供应块，用于响应输入的控制信号向半导体存储器件提供第一电压; 以及第二电压供应块，用于响应于输入的控制信号向半导体存储器件提供第二电压，其中第一和第二电压被用作包括在半导体存储器件中的晶体管的体电压。

公开(公告)号：US09368237B2

公开(公告)日：2016-06-14

申请号：US12483372

申请日：2009-06-12

申请人： Sun Mo An ,  Shin Ho Chu

发明人： Sun Mo An ,  Shin Ho Chu

IPC分类号： G11C29/46

CPC分类号： G11C29/46

摘要： A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state.

摘要翻译： 提出了能够控制测试模式而不停止半导体集成电路测试的半导体集成电路。 半导体集成电路包括：测试模式控制单元，被配置为响应于地址解码信号产生第一组的多个测试模式信号和第二组的多个测试模式信号。 测试模式控制单元通过使用第二组的测试模式信号提供复位信号来选择性地使第一组的测试模式信号失效。 因此，可以通过使用复位信号使先前的测试模式失效并且通过执行新的测试模式而不断开测试模式状态来减少半导体集成电路的测试时间。

公开(公告)号：US08767489B2

公开(公告)日：2014-07-01

申请号：US13412982

申请日：2012-03-06

申请人： Myung Hwan Lee ,  Shin Ho Chu

发明人： Myung Hwan Lee ,  Shin Ho Chu

IPC分类号： G11C29/00 ,  G11C17/16

CPC分类号： G11C29/808 ,  G11C17/16 ,  G11C29/785 ,  G11C29/787

摘要： A semiconductor memory device includes a transmission line configured to transmit a fuse enable signal for performance of a repair operation; a first repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a first repair enable signal for performing a repair operation for a first bank; and a second repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a second repair enable signal for performing a repair operation for a second bank.

摘要翻译： 一种半导体存储器件，包括：传输线，用于传输用于执行修复操作的熔丝使能信号; 第一修复使能信号生成单元，被配置为通过传输线接收熔丝使能信号，并生成用于执行第一存储体的修复操作的第一修复使能信号; 以及第二修复使能信号生成单元，被配置为通过传输线接收熔丝使能信号，并产生用于执行第二存储体的修复操作的第二修复使能信号。