公开(公告)号：US06269435B1

公开(公告)日：2001-07-31

申请号：US09152944

申请日：1998-09-14

申请人： William J. Dally ,  Scott Whitney Rixner ,  John Owens ,  Ujval J. Kapasi

发明人： William J. Dally ,  Scott Whitney Rixner ,  John Owens ,  Ujval J. Kapasi

IPC分类号： G06F9305

CPC分类号： G06F9/3885 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3842 ,  G06F9/3879 ,  G06F9/3891 ,  G06F15/8084

摘要： A processor implements conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed is divided into two groups based on whether or not they satisfy a given condition by, e.g., steering each to one of two index vectors. Once the data has been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication.

摘要翻译： 处理器实现条件向量操作，其中基于条件向量将包含要在条件操作中使用的多个操作数的输入向量划分为两个或更多个输出向量。 然后可以以全处理器效率处理每个输出向量，而不会由于分支延迟而浪费周期。 基于它们是否满足给定条件，待处理的数据被分成两组，例如通过将其转换为两个索引向量中的一个。 一旦以这种方式隔离了数据，可以执行后续处理，而无需条件操作，由于分支延迟浪费处理器周期，由于预测导致不正确的推测或不必要的指令的执行。

公开(公告)号：US06192384B1

公开(公告)日：2001-02-20

申请号：US09152763

申请日：1998-09-14

申请人： William J. Dally ,  Scott Whitney Rixner ,  Jeffrey P. Grossman ,  Christopher James Buehler

发明人： William J. Dally ,  Scott Whitney Rixner ,  Jeffrey P. Grossman ,  Christopher James Buehler

IPC分类号： G06F928

CPC分类号： G06F9/3891 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3879 ,  G06F9/3885 ,  G06F15/8084

摘要： A processor particularly useful in multimedia applications such as image processing is based on a stream programming model and has a tiered storage architecture to minimize global bandwidth requirements. The processor has a stream register file through which the processor's functional units transfer streams to execute processor operations. Load and store instructions transfer streams between the stream register file and a stream memory; send and receive instructions transfer streams between stream register files of different processors; and operate instructions pass streams between the stream register file and computational kernels. Each of the computational kernels is capable of performing compound vector operations. A compound vector operation performs a sequence of arithmetic operations on data read from the stream register file, i.e., a global storage resource, and generates a result that is written back to the stream register file. Each function or compound vector operation is specified by an instruction sequence that specifies the arithmetic operations and data movements that are performed each cycle to carry out the compound operation. This sequence can, for example, be specified using microcode.

摘要翻译： 在诸如图像处理的多媒体应用中特别有用的处理器基于流编程模型，并且具有分层存储架构以最小化全局带宽要求。 处理器具有流寄存器文件，处理器的功能单元通过该寄存器文件传送流以执行处理器操作。 加载和存储指令在流注册文件和流存储器之间传输流; 发送和接收指令在不同处理器的流注册文件之间传输流; 并且操作指令在流寄存器文件和计算内核之间传递流。 每个计算内核都能执行复合向量操作。 复合向量操作对从流寄存器文件即全局存储资源读取的数据执行算术运算序列，并生成写回到流寄存器文件的结果。 每个功能或复合向量操作由指定序列指定，该指令序列指定每个周期执行的执行复合操作的算术运算和数据移动。 例如，可以使用微码来指定该序列。