公开(公告)号：US20220284946A1

公开(公告)日：2022-09-08

申请号：US17678500

申请日：2022-02-23

申请人： Sang-Seok Kang ,  Young-Hee Jung ,  Sun-Young LEE

发明人： Sang-Seok Kang ,  Young-Hee Jung ,  Sun-Young LEE

IPC分类号： G11C11/4093 ,  G11C5/04 ,  G11C11/408 ,  G11C11/4096

摘要： Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.

公开(公告)号：US08477553B2

公开(公告)日：2013-07-02

申请号：US13020450

申请日：2011-02-03

申请人： Sang-Seok Kang ,  Sang-Man Byun ,  Jae-Hoon Joo

发明人： Sang-Seok Kang ,  Sang-Man Byun ,  Jae-Hoon Joo

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  H01H37/76

摘要： Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

摘要翻译： 提供了能够根据操作模式选择性地使用用于逻辑运算的电源电压的熔丝电路。 熔丝电路包括模式产生电路，电源电压选择电路和至少一个保险丝单元。 模式产生电路产生多个模式信号。 电源电压选择电路响应于多个模式信号选择多个电源电压中的一个，并将所选择的电源电压输出到第一节点。 每个熔丝单元耦合在第一节点和地电压之间，并且使用所选择的电源电压作为用于逻辑运算的电源电压。 因此，包括熔丝电路的半导体装置可以精确地测试熔丝的连接状态。

公开(公告)号：US08411520B2

公开(公告)日：2013-04-02

申请号：US12654739

申请日：2009-12-30

申请人： Myung-Jae Lee ,  Sang Seok Kang ,  Jong Hyoung Lim

发明人： Myung-Jae Lee ,  Sang Seok Kang ,  Jong Hyoung Lim

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C5/14 ,  G11C7/1045 ,  G11C7/14 ,  G11C7/22 ,  G11C8/12

摘要： A semiconductor memory device comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, a standby current measuring unit configured to measure a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines. Each of the standby currents is generated by each of the bias voltages applied by the bias application unit.

摘要翻译： 一种半导体存储器件，包括：包括多个位线和多个虚拟位线的存储器阵列;偏置施加单元，被配置为向所述多个虚拟位线提供具有多个电压电平的偏置电压;待机电流测量单元 被配置为测量所述多个位线中的至少一个与所述多个虚拟位线中的至少一个之间的待机电流中的至少一个的值。 每个待机电流由偏置施加单元施加的每个偏置电压产生。

公开(公告)号：US20120063251A1

公开(公告)日：2012-03-15

申请号：US13228102

申请日：2011-09-08

申请人： Jong Hyoung LIM ,  Sang Seok Kang ,  Hyung Shin Kwon

发明人： Jong Hyoung LIM ,  Sang Seok Kang ,  Hyung Shin Kwon

IPC分类号： G11C7/06

CPC分类号： G11C7/12

摘要： A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.

摘要翻译： 半导体器件包括位线，互补位线，被配置为感测和放大位线和互补位线之间的电压差的读出放大器，以及电容调整电路，配置为调整互补位线的负载电容 响应于多个控制信号。

公开(公告)号：US08102689B2

公开(公告)日：2012-01-24

申请号：US12687971

申请日：2010-01-15

申请人： Min-Ki Hong ,  Sang-Seok Kang ,  Dong-Min Kim

发明人： Min-Ki Hong ,  Sang-Seok Kang ,  Dong-Min Kim

IPC分类号： G11C5/02

CPC分类号： G11C11/4091 ,  G11C11/4097

摘要： A semiconductor memory device having dummy sense amplifiers and a method of utilizing the same are provided. Embodiments of the semiconductor memory device may include at least one dummy cell block including dummy cells and memory cells. Normal bit lines connecting the memory cells in the dummy cell block in a first direction and dummy bit lines connecting the dummy cells in the first direction. A dummy sense amplifier is also included for connecting any two of the normal bit lines and the dummy bit lines. Some of the embodiments may improve the sensing margin and refresh margin in sensing memory cells in the dummy cell, as well as increasing the redundancy efficiency and utilization of the dummy cells.

摘要翻译： 提供了具有虚拟读出放大器的半导体存储器件及其利用方法。 半导体存储器件的实施例可以包括至少一个虚设单元块，其包括虚设单元和存储单元。 在第一方向连接虚拟单元块中的存储单元的正常位线和在第一方向上连接虚设单元的虚拟位线。 还包括虚拟读出放大器，用于连接任何两个正常位线和虚拟位线。 一些实施例可以改善感测虚拟单元中的存储器单元的感测容限和刷新余量，以及提高冗余效率和虚拟单元的利用。

公开(公告)号：US08015459B2

公开(公告)日：2011-09-06

申请号：US12654644

申请日：2009-12-28

申请人： Jong-Hyoung Lim ,  Sang-Seok Kang

发明人： Jong-Hyoung Lim ,  Sang-Seok Kang

IPC分类号： G11C29/00

CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C7/1096 ,  G11C11/4096

摘要： A semiconductor memory device and method directed to performing a memory operation in a semiconductor memory device are provided. The method includes receiving a write command signal from a memory controller; receiving data from the memory controller, the data including n pieces of data, wherein the k-th piece of data comprises masking data to be masked; and receiving a data masking signal from the memory controller, the data masking signal including enable information that enables data masking, and non-enable information for not enabling data masking, wherein the enable information is used to mask the k-th piece of data. A latency between receiving the write command signal and receiving the enable information is less than a latency between receiving the write command and receiving the k-th piece of data.

摘要翻译： 提供一种半导体存储器件和方法，用于在半导体存储器件中执行存储器操作。 该方法包括从存储器控制器接收写命令信号; 从所述存储器控制器接收数据，所述数据包括n条数据，其中所述第k条数据包括要屏蔽的掩蔽数据; 以及从所述存储器控制器接收数据屏蔽信号，所述数据屏蔽信号包括启用数据屏蔽的使能信息，以及不启用数据屏蔽的非使能信息，其中所述使能信息用于掩蔽所述第k条数据。 接收写命令信号和接收使能信息之间的等待时间小于接收写命令和接收第k条数据之间的等待时间。

公开(公告)号：US20100246300A1

公开(公告)日：2010-09-30

申请号：US12731749

申请日：2010-03-25

申请人： Jong-Hyun Choi ,  Sang-Seok Kang

发明人： Jong-Hyun Choi ,  Sang-Seok Kang

IPC分类号： G11C29/00 ,  G11C7/12

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/1204

摘要： A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括耦合到第一位线和字线的第一存储器单元，以及耦合到第二位线和字线并且邻近第一存储单元设置的第二存储单元。 控制器电路被配置为分别向第一和第二位线提供第一和第二预充电电压。 第一预充电电压被提供为正电源电压，并且在老化测试操作期间将第二预充电电压设置为负应力电压。 还讨论了相关的操作方法。

公开(公告)号：US20100118633A1

公开(公告)日：2010-05-13

申请号：US12687971

申请日：2010-01-15

申请人： Min-Ki HONG ,  Sang-Seok Kang ,  Dong-Min Kim

发明人： Min-Ki HONG ,  Sang-Seok Kang ,  Dong-Min Kim

IPC分类号： G11C7/02 ,  G11C8/00

CPC分类号： G11C11/4091 ,  G11C11/4097

摘要： A semiconductor memory device having dummy sense amplifiers and a method of utilizing the same are provided. Embodiments of the semiconductor memory device may include at least one dummy cell block including dummy cells and memory cells. Normal bit lines connecting the memory cells in the dummy cell block in a first direction and dummy bit lines connecting the dummy cells in the first direction. A dummy sense amplifier is also included for connecting any two of the normal bit lines and the dummy bit lines. Some of the embodiments may improve the sensing margin and refresh margin in sensing memory cells in the dummy cell, as well as increasing the redundancy efficiency and utilization of the dummy cells.

摘要翻译： 提供了具有虚拟读出放大器的半导体存储器件及其利用方法。 半导体存储器件的实施例可以包括至少一个虚设单元块，其包括虚设单元和存储单元。 在第一方向连接虚拟单元块中的存储单元的正常位线和在第一方向上连接虚设单元的虚拟位线。 还包括虚拟读出放大器，用于连接任何两个正常位线和虚拟位线。 一些实施例可以改善感测虚拟单元中的存储器单元的感测容限和刷新余量，以及提高冗余效率和虚拟单元的利用。

公开(公告)号：US07649760B2

公开(公告)日：2010-01-19

申请号：US11465304

申请日：2006-08-17

申请人： Min-Ki Hong ,  Sang-Seok Kang ,  Dong-Min Kim

发明人： Min-Ki Hong ,  Sang-Seok Kang ,  Dong-Min Kim

IPC分类号： G11C5/02

CPC分类号： G11C11/4091 ,  G11C11/4097

摘要： A semiconductor memory device having dummy sense amplifiers and a method of utilizing the same are provided. Embodiments of the semiconductor memory device may include at least one dummy cell block including dummy cells and memory cells. Normal bit lines connecting the memory cells in the dummy cell block in a first direction and dummy bit lines connecting the dummy cells in the first direction. A dummy sense amplifier is also included for connecting any two of the normal bit lines and the dummy bit lines. Some of the embodiments may improve the sensing margin and refresh margin in sensing memory cells in the dummy cell, as well as increasing the redundancy efficiency and utilization of the dummy cells.

摘要翻译： 提供了具有虚拟读出放大器的半导体存储器件及其利用方法。 半导体存储器件的实施例可以包括至少一个虚设单元块，其包括虚设单元和存储单元。 在第一方向连接虚拟单元块中的存储单元的正常位线和在第一方向上连接虚设单元的虚拟位线。 还包括虚拟读出放大器，用于连接任何两个正常位线和虚拟位线。 一些实施例可以改善感测虚拟单元中的存储器单元的感测容限和刷新余量，以及提高冗余效率和虚拟单元的利用。

公开(公告)号：US07624317B2

公开(公告)日：2009-11-24

申请号：US11709689

申请日：2007-02-23

申请人： Sang-Man Byun ,  Sang-Seok Kang

发明人： Sang-Man Byun ,  Sang-Seok Kang

IPC分类号： G11C29/00

CPC分类号： G11C29/40 ,  G11C2029/4002

摘要： A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory block in parallel and comparing the two bits output from each memory block with each other in a first test mode, and outputting two bits from respectively different memory blocks and comparing the two bits output from the respectively different memory blocks with each other in a second test mode.

摘要翻译： 半导体存储器件通过将测试图案数据写入到多个存储块中来对多个存储块执行并行位测试，并行地从每个存储块输出两个比特，并将每个存储器块输出的两个比较 第一测试模式，并且从第二测试模式中分别输出来自不同存储器块的两个比特并将来自各个不同存储块的两比特输出进行比较。