公开(公告)号：US5416691A

公开(公告)日：1995-05-16

申请号：US177589

申请日：1994-01-05

Applicant: Rosamaria Croughwell

Inventor： Rosamaria Croughwell

IPC: H03L7/089 ,  H03L7/00

CPC classification number: H03L7/0895

Abstract: An improved charge pump circuit includes a charge pump capacitor having first and second terminals for charging in first and second polarities; a current source device for supplying current selectively to the charge pump capacitor through the first and second terminals; a clamping device for defining first and second clamping voltages for the first and second terminals, respectively; a switching device for selectively connecting the current source device to one of the terminals and connecting the clamping device to the other of the terminals; and a clamp control device, responsive to the differential mode voltage across the charge pump capacitor, for setting the clamping voltages to obtain a difference between the clamping voltages equal to said differential mode voltage and pumping equal charge into the charge pump capacitor in either polarity.

Abstract translation: 改进的电荷泵电路包括具有用于以第一和第二极性充电的第一和第二端子的电荷泵电容器; 用于通过第一和第二端子选择性地向电荷泵电容器提供电流的电流源装置; 用于分别为第一和第二端子定义第一和第二钳位电压的钳位装置; 开关装置，用于选择性地将电流源装置连接到端子之一并将夹持装置连接到另一个端子; 以及钳位控制装置，其响应于电荷泵电容器两端的差分模式电压，用于设定钳位电压以获得等于所述差分模式电压的钳位电压之间的差值，并且以任一极性将等电荷泵送到电荷泵电容器中。

公开(公告)号：US06560305B1

公开(公告)日：2003-05-06

申请号：US09168369

申请日：1998-10-07

Applicant: Rosamaria Croughwell

Inventor： Rosamaria Croughwell

IPC: H03D324

CPC classification number: H03L7/085

Abstract: A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data. The system includes a voltage controlled oscillator for producing the clock pulses. The frequency of such clock pulses changes in accordance with a control signal. Each one of the clock pulses has four sequential, one-quarter period phases. Adjacent phases are separated by boundaries to divide each clock pulse period into four quadrants. A frequency detector is fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data. A lock-out circuit prevents subsequent production of the control signal until a subsequently detected data edge crosses a different one of the boundaries.

Abstract translation: 一种用于产生频率等于二进制数据流的频率的时钟脉冲的频率检测系统。 该系统包括用于产生时钟脉冲的压控振荡器。 这种时钟脉冲的频率根据控制信号而变化。 每个时钟脉冲具有四个连续的四分之一周期相位。 相邻相位被边界分隔，以将每个时钟脉冲周期分成四个象限。 频率检测器由二进制数据流的检测边缘和用于产生控制信号的时钟脉冲馈送，根据时钟脉冲的频率与二进制数据流的频率之间的频率差。 锁定电路防止后续产生控制信号，直到随后检测到的数据沿跨越不同的边界。

公开(公告)号：US06400227B1

公开(公告)日：2002-06-04

申请号：US09871446

申请日：2001-05-31

Applicant: Marc Goldfarb ,  Rosamaria Croughwell ,  Peter Katzin

Inventor： Marc Goldfarb ,  Rosamaria Croughwell ,  Peter Katzin

IPC: H03F368

CPC classification number: H03F1/223 ,  H03F3/72 ,  H03F2200/306 ,  H03G1/0017 ,  H03G1/0088

Abstract: A variable gain amplifier has at least two branches connected in parallel to drive a common output load. Each branch includes at least two FETs in a cascode configuration. A first FET in each branch is arranged to receive an input signal and to amplify the signal in a common source configuration; the second FET is arranged in a common gate configuration with its source receiving the output current of the first FET. The gate of the second FET is coupled to a corresponding gain control input so that the second FET is enabled when the gate receives an enabling gain control signal and disabled otherwise. Preferably the first and second FETs in each branch are biased in a saturation region of operation when the second FET is enabled by the gain control input. This maintains a low distortion figure throughout the dynamic range of the gain control. Preferably, the invention also includes an active fixed gain power amplification stage for coupling the output to a power amplifier.

Abstract translation: 可变增益放大器具有并联连接的至少两个分支以驱动公共输出负载。 每个分支包括至少两个共源共栅配置的FET。 每个分支中的第一FET被布置成接收输入信号并且以公共源配置放大信号; 第二FET被布置成共用栅极配置，其源极接收第一FET的输出电流。 第二FET的栅极耦合到相应的增益控制输入，使得第二FET在栅极接收到使能增益控制信号时使能，否则禁用。 优选地，当通过增益控制输入使能第二FET时，每个分支中的第一和第二FET被偏置在饱和操作区域中。 这在增益控制的整个动态范围内保持低失真。 优选地，本发明还包括用于将输出耦合到功率放大器的有源固定增益功率放大级。