MATERIALS AND METHODS FOR SUPPRESSING INFLAMATORY AND NEUROPATHIC PAIN
    3.
    发明申请
    MATERIALS AND METHODS FOR SUPPRESSING INFLAMATORY AND NEUROPATHIC PAIN 有权
    用于抑制炎症和神经痛疼痛的材料和方法

    公开(公告)号:US20130210698A1

    公开(公告)日:2013-08-15

    申请号:US13703181

    申请日:2011-06-10

    申请人: Rajesh Khanna

    发明人: Rajesh Khanna

    IPC分类号: C07K14/005

    摘要: N-type voltage-gated calcium channels (CaV2.2) are critical mediators of neurotransmitter release and are thought to be involved with transmission of nociception. The use of conventional CaV2.2 blockers in pain therapeutics is limited by side effects. Reported herein is a means to suppress both inflammatory and neuropathic pain without directly blocking CaV2.2, but rather by inhibiting the binding of the axonal collapsin response mediator protein 2 (CRMP-2), a protein known to enhance CaV2.2 function. A 15 amino acid peptide of CRMP-2 fused to the protein transduction domain of the HIV tat protein (TAT CBD3) reduced meningeal blood flow induced by activation of the trigeminovascular system, prevented inflammation-induced tactile hypernociception induced by intraplantar formalin and nocifensive behavior following corneal capsaicin application, and reversed neuropathic hypernociception produced by the antiretroviral drug 2′,3′-dideoxycytidine. Preventing CRMP-2—mediated enhancement of CaV2.2 function suppressed inflammatory and neuropathic nociception, providing a method for treating pain and inflammation.

    摘要翻译: N型电压门控钙通道(CaV2.2)是神经递质释放的关键介质,被认为与伤害感染的传播有关。 常规的CaV2.2阻滞剂在疼痛治疗中的应用受到副作用的限制。 本文报道的是抑制炎症和神经性疼痛而不直接阻断CaV2.2的手段,而是通过抑制已知增强CaV2.2功能的蛋白质的轴突折叠蛋白酶应答介质蛋白2(CRMP-2)的结合来抑制。 融合到HIV tat蛋白(TAT CBD3)的蛋白转导结构域的CRMP-2的15个氨基酸的肽减少了由三叉神经血管系统的激活引起的脑膜血流,防止了由板内福尔马林引起的炎症诱发的触觉性超敏感性和下列不良反应行为 角膜辣椒素应用,以及由抗逆转录病毒药物2',3'-双脱氧胞苷产生的逆转神经性超敏感性。 预防CRMP-2介导的CaV2.2功能的增强抑制炎症和神经病理伤害感受,提供治疗疼痛和炎症的方法。

    Selectively reducing transistor channel length in a semiconductor device
    7.
    发明授权
    Selectively reducing transistor channel length in a semiconductor device 有权
    在半导体器件中选择性地减小晶体管沟道长度

    公开(公告)号:US06427226B1

    公开(公告)日:2002-07-30

    申请号:US09318782

    申请日:1999-05-25

    IPC分类号: G06F1750

    CPC分类号: G06F17/5031 G06F17/505

    摘要: Tools and techniques used in conjunction with integrated circuit path timing information can selectively reduce the channel length of transistors in cells associated with the most critical paths in an integrated circuit, while keeping the overall integrated circuit design within a specified power budget. Moreover, by targeting pins of cells (and thus their associated transistors) that are used by multiple paths, and/or that offer the greatest potential speed improvement, timing violations along critical paths can be reduced or eliminated with a relatively few number of replacements. Paths within a certain timing violation range are selected for analysis. The pins within those paths are ranked by pin criticality, which can depend on, for example, the number of times a particular pin occurs in any path, the timing enhancement associated with replacing a cell having that pin, and the impact of replacing a cell having that pin would have on the power budget. Transistors within cells (or entire cells) associated with pins are replaced based on the pin criticality until timing improvements are sufficient to remove a path from the range of paths being examined. Successive paths, and ranges of paths are analyzed until the power budget is exceeded, or no more improvements can be made.

    摘要翻译: 与集成电路路径定时信息一起使用的工具和技术可以选择性地减少与集成电路中最关键路径相关联的单元中的晶体管的沟道长度,同时将整体集成电路设计保持在规定的功率预算范围内。 此外,通过针对由多个路径使用的单元(以及因此它们相关的晶体管)的引脚和/或提供最大的潜在速度改进,可以以相对较少数量的替换来减少或消除沿关键路径的定时违例。 选择某一定时违规范围内的路径进行分析。 这些路径内的引脚按引脚关键度进行排序,这可能取决于例如特定引脚在任何路径中发生的次数,与替换具有该引脚的单元相关联的时序增强以及替换单元的影响 有这个引脚将具有功率预算。 基于引脚关键性,更换与引脚相关的单元(或整个单元)内的晶体管,直到时序改进足以从正在检查的路径的范围中移除路径。 分析连续路径和路径范围,直到超出功率预算,或者不能进行更多改进。

    Fast tag compare and bank select in set associative cache
    8.
    发明授权
    Fast tag compare and bank select in set associative cache 失效
    快速标签比较和集合相关缓存中的存储区选择

    公开(公告)号:US5353424A

    公开(公告)日:1994-10-04

    申请号:US794865

    申请日:1991-11-19

    IPC分类号: G06F12/08

    CPC分类号: G06F12/0895 G06F12/0864

    摘要: A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled. The comparator is in large part self-timed using a flow-through design, as distinguished from being enabled on clock edges. Delay elements in the bank select logic allow the banks to be timed against each other, and current limiters are employed to equalize the timing of miss signals, regardless of the number of match lines switching high (which is data dependent). An address producing 19-of-20 match bits will result in a NOR gate output of about the same timing as an address producing no match bits, even though the former will turn on only one transistor to discharge the precharged output node of the NOR gate, whereas the later will turn on twenty paths for discharge. Although a two-way set associative cache is shown herein as an example embodiment, one of the features of the invention is that higher levels of associativity, e.g., four-way and eight-way, are equally well accommodated.

    摘要翻译: 用于计算机系统中的组相关高速缓存的标签比较器和存储体选择器在最小时间内操作,使得在存储器周期中早期产生高速缓存命中或未命中信号。 高速缓存的数据存储器具有两个(或更多个)存储体,每个存储体具有标签存储,并且当标签转换正在进行时,使用索引(低位地址位)分开存取和并行访问两个存储体。 执行两个逐位标签比较,每个标签存储一个,产生两个多位匹配指示,每个标签存储中每个标签位一位。 这两个匹配指示被应用于两个单独的动态NOR门,并且两个输出被施加到逻辑电路以检测命中并产生一个存储体选择输出。 比较操作有四个可能的结果:两家银行错失,左岸点击,右岸点击,两家银行都受到打击。 后面的条件表示可能的模糊性,并且都不应该使用数据项,所以发出了错误信号。 使用流通设计,比较器在很大程度上是自定时的,与时钟边沿不同。 银行选择逻辑中的延迟元素允许银行彼此定时,并且采用电流限制器来均衡缺失信号的定时,而不管匹配线的数量如何切换高(这取决于数据)。 产生20位20位匹配位的地址将导致与不产生不匹配位的地址大致相同的定时的或非门输出,即使前者将仅接通一个晶体管来放电NOR门的预充电输出节点 ,而后来将打开二十条出路。 尽管本文中示出了双向组关联高速缓存作为示例实施例,但是本发明的特征之一是更高级别的关联性,例如四路和八路同样适应。

    Materials and methods for suppressing inflammatory and neuropathic pain
    9.
    发明授权
    Materials and methods for suppressing inflammatory and neuropathic pain 有权
    抑制炎性和神经性疼痛的材料和方法

    公开(公告)号:US09018173B2

    公开(公告)日:2015-04-28

    申请号:US13703181

    申请日:2011-06-10

    申请人: Rajesh Khanna

    发明人: Rajesh Khanna

    摘要: N-type voltage-gated calcium channels (CaV2.2) are critical mediators of neurotransmitter release and are thought to be involved with transmission of nociception. The use of conventional CaV2.2 blockers in pain therapeutics is limited by side effects. Reported herein is a means to suppress both inflammatory and neuropathic pain without directly blocking CaV2.2, but rather by inhibiting the binding of the axonal collapsin response mediator protein 2 (CRMP-2), a protein known to enhance CaV2.2 function. A 15 amino acid peptide of CRMP-2 fused to the protein transduction domain of the HIV tat protein (TAT CBD3) reduced meningeal blood flow induced by activation of the trigeminovascular system, prevented inflammation-induced tactile hypernociception induced by intraplantar formalin and nocifensive behavior following corneal capsaicin application, and reversed neuropathic hypernociception produced by the antiretroviral drug 2′,3′-dideoxycytidine. Preventing CRMP-2—mediated enhancement of CaV2.2 function suppressed inflammatory and neuropathic nociception, providing a method for treating pain and inflammation.

    摘要翻译: N型电压门控钙通道(CaV2.2)是神经递质释放的关键介质,被认为与伤害感染的传播有关。 常规的CaV2.2阻滞剂在疼痛治疗中的应用受到副作用的限制。 本文报道的是抑制炎症和神经性疼痛而不直接阻断CaV2.2的手段,而是通过抑制已知增强CaV2.2功能的蛋白质的轴突折叠蛋白酶应答介质蛋白2(CRMP-2)的结合来抑制。 融合到HIV tat蛋白(TAT CBD3)的蛋白转导结构域的CRMP-2的15个氨基酸的肽减少了由三叉神经血管系统的激活引起的脑膜血流,防止了由板内福尔马林引起的炎症诱发的触觉性超敏感性和下列不良反应行为 角膜辣椒素应用,以及由抗逆转录病毒药物2',3'-双脱氧胞苷产生的逆转神经性超敏感性。 预防CRMP-2介导的CaV2.2功能的增强抑制炎症和神经病理伤害感受,提供治疗疼痛和炎症的方法。

    HEART VALVE DELIVERY SYSTEM WITH VALVE CATHETER
    10.
    发明申请
    HEART VALVE DELIVERY SYSTEM WITH VALVE CATHETER 审中-公开
    带阀门的心瓣输送系统

    公开(公告)号:US20120290078A1

    公开(公告)日:2012-11-15

    申请号:US13449200

    申请日:2012-04-17

    IPC分类号: A61F2/24

    摘要: A heart valve delivery system is provided wherein a prosthetic valve is carried on a valve catheter inside a tubular delivery sleeve. The valve catheter has a distal end coupled to a mop. The mop comprises a plurality of flexible extensions configured for releasable attachment to the prosthetic valve. A lead screw nut is coupled to a proximal end of the tubular delivery sleeve and a lead screw is coupled to the valve catheter. The lead screw engages the lead screw nut and rotation of the lead screw causes the delivery sleeve to retract relative to the valve catheter and the prosthetic valve for exposing the prosthetic valve. The flexible extensions of the mop allow expansion of the valve while maintaining the attachment during placement of the valve at a native valve site.

    摘要翻译: 提供心脏瓣膜输送系统,其中人造瓣膜被承载在管状输送套筒内的阀导管上。 阀导管具有与拖把相连的远端。 拖把包括多个柔性延伸部,其构造成用于可释放地附接到人工瓣膜。 导螺杆螺母联接到管状输送套筒的近端,并且导螺杆联接到瓣膜导管。 导螺杆与导螺杆螺母接合并且导螺杆的旋转使得输送套筒相对于阀导管和用于暴露人造瓣膜的假肢瓣缩回。 拖把的柔性延伸部件可以在将瓣膜置于自然瓣膜部位的同时保持附件的同时扩张阀。